Commit 1ad9767a authored by Marc Zyngier's avatar Marc Zyngier
Browse files

KVM: arm64: Add trap routing for GMID_EL1 

HCR_EL2.TID5 is currently ignored by the trap routing infrastructure.
Wire it in the routing table so that GMID_EL1, the sole register
trapped by this bit, is correctly handled in the NV case.

Link: https://patch.msgid.link/20260108173233.2911955-3-maz@kernel.org


Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
parent 4a7fe842

arch/arm64/kvm/emulate-nested.c

+8 −0
Original line number Diff line number Diff line
@@ -70,6 +70,7 @@ enum cgt_group_id { 
	CGT_HCR_ENSCXT,

	CGT_HCR_TTLBIS,

	CGT_HCR_TTLBOS,

	CGT_HCR_TID5,



	CGT_MDCR_TPMCR,

	CGT_MDCR_TPM,
@@ -308,6 +309,12 @@ static const struct trap_bits coarse_trap_bits[] = { 
		.mask		= HCR_TTLBOS,

		.behaviour	= BEHAVE_FORWARD_RW,

	},

	[CGT_HCR_TID5] = {

		.index		= HCR_EL2,

		.value		= HCR_TID5,

		.mask		= HCR_TID5,

		.behaviour	= BEHAVE_FORWARD_RW,

	},

	[CGT_MDCR_TPMCR] = {

		.index		= MDCR_EL2,

		.value		= MDCR_EL2_TPMCR,
@@ -665,6 +672,7 @@ static const struct encoding_to_trap_config encoding_to_cgt[] __initconst = { 
	SR_TRAP(SYS_CCSIDR2_EL1,	CGT_HCR_TID2_TID4),

	SR_TRAP(SYS_CLIDR_EL1,		CGT_HCR_TID2_TID4),

	SR_TRAP(SYS_CSSELR_EL1,		CGT_HCR_TID2_TID4),

	SR_TRAP(SYS_GMID_EL1,		CGT_HCR_TID5),

	SR_RANGE_TRAP(SYS_ID_PFR0_EL1,

		      sys_reg(3, 0, 0, 7, 7), CGT_HCR_TID3),

	SR_TRAP(SYS_ICC_SGI0R_EL1,	CGT_HCR_IMO_FMO_ICH_HCR_TC),