Commit 1c83601b authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'mips_6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux 

Pull MIPS updates from Thomas Bogendoerfer:

 - Add support for multi-cluster configuration

 - Add quirks for enabling multi-cluster mode on EyeQ6

 - Add DTS clocks for ralink

 - Cleanup realtek DTS

 - Other cleanups and fixes

* tag 'mips_6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (35 commits)
  MIPS: config: omega2+, vocore2: enable CLK_MTMIPS
  arch: mips: defconfig: Drop obsolete CONFIG_NET_CLS_TCINDEX
  MIPS: cm: Fix warning if MIPS_CM is disabled
  MIPS: Fix Macro name
  MIPS: ds1287: Match ds1287_set_base_clock() function types
  MIPS: cevt-ds1287: Add missing ds1287.h include
  MIPS: dec: Declare which_prom() as static
  MIPS: Loongson2ef: Replace deprecated strncpy() with strscpy()
  mips: dts: ralink: mt7628a: update system controller node and its consumers
  mips: dts: ralink: mt7620a: update system controller node and its consumers
  mips: dts: ralink: rt3883: update system controller node and its consumers
  mips: dts: ralink: rt3050: update system controller node and its consumers
  mips: dts: ralink: rt2880: update system controller node and its consumers
  dt-bindings: clock: add clock definitions for Ralink SoCs
  MIPS: Use arch specific syscall name match function
  mips: dts: realtek: Add restart to Cisco SG220-26P
  mips: dts: realtek: Add RTL838x SoC peripherals
  mips: dts: realtek: Replace uart clock property
  mips: dts: realtek: Correct uart interrupt-parent
  mips: dts: realtek: Add SoC IRQ node for RTL838x
  ...
parents f90f2145 855912be

Documentation/devicetree/bindings/clock/mediatek,mtmips-sysc.yaml

+10 −1
Original line number Diff line number Diff line
@@ -18,6 +18,12 @@ description: | 
  These SoCs have an XTAL from where the cpu clock is

  provided as well as derived clocks for the bus and the peripherals.



  Each clock is assigned an identifier and client nodes use this identifier

  to specify the clock which they consume.



  All these identifiers could be found in:

  [1]: <include/dt-bindings/clock/mediatek,mtmips-sysc.h>.



properties:

  compatible:

    items:
@@ -38,7 +44,8 @@ properties: 


  '#clock-cells':

    description:

      The first cell indicates the clock number.

      The first cell indicates the clock number, see [1] for available

      clocks.

    const: 1



  '#reset-cells':
@@ -56,6 +63,8 @@ additionalProperties: false 


examples:

  - |

    #include <dt-bindings/clock/mediatek,mtmips-sysc.h>



    syscon@0 {

      compatible = "ralink,rt5350-sysc", "syscon";

      reg = <0x0 0x100>;

Documentation/devicetree/bindings/mips/mti,mips-cm.yaml

0 → 100644
+57 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/mips/mti,mips-cm.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: MIPS Coherence Manager



description:

  The Coherence Manager (CM) is responsible for establishing the

  global ordering of requests from all elements of the system and

  sending the correct data back to the requester. It supports Cache

  to Cache transfers.

  https://training.mips.com/cps_mips/PDF/CPS_Introduction.pdf

  https://training.mips.com/cps_mips/PDF/Coherency_Manager.pdf



maintainers:

  - Jiaxun Yang <jiaxun.yang@flygoat.com>



properties:

  compatible:

    oneOf:

      - const: mti,mips-cm

      - const: mobileye,eyeq6-cm

        description:

          On EyeQ6 the HCI (Hardware Cache Initialization) information for

          the L2 cache in multi-cluster configuration is broken.



  reg:

    description:

      Base address and size of the Global Configuration Registers

      referred to as CMGCR.They are the system programmer's interface

      to the Coherency Manager. Their location in the memory map is

      determined at core build time. In a functional system, the base

      address is provided by the Coprocessor 0, but some

      System-on-Chip (SoC) designs may not provide an accurate address

      that needs to be described statically.



    maxItems: 1



required:

  - compatible



additionalProperties: false



examples:

  - |

    coherency-manager@1fbf8000 {

      compatible = "mti,mips-cm";

      reg = <0x1bde8000 0x8000>;

    };



  - |

    coherency-manager {

      compatible = "mobileye,eyeq6-cm";

    };

...

arch/mips/boot/dts/ingenic/gcw0.dts

+1 −1
Original line number Diff line number Diff line
@@ -91,7 +91,7 @@ sound { 
			"MIC1N", "Built-in Mic";

		simple-audio-card,pin-switches = "Speaker", "Headphones";



		simple-audio-card,hp-det-gpio = <&gpf 21 GPIO_ACTIVE_LOW>;

		simple-audio-card,hp-det-gpios = <&gpf 21 GPIO_ACTIVE_LOW>;

		simple-audio-card,aux-devs = <&speaker_amp>, <&headphones_amp>;



		simple-audio-card,bitclock-master = <&dai_codec>;

arch/mips/boot/dts/ingenic/rs90.dts

+1 −1
Original line number Diff line number Diff line
@@ -148,7 +148,7 @@ sound { 
			"Speaker", "OUTR";

		simple-audio-card,pin-switches = "Speaker";



		simple-audio-card,hp-det-gpio = <&gpd 16 GPIO_ACTIVE_LOW>;

		simple-audio-card,hp-det-gpios = <&gpd 16 GPIO_ACTIVE_LOW>;

		simple-audio-card,aux-devs = <&amp>;



		simple-audio-card,bitclock-master = <&dai_codec>;

arch/mips/boot/dts/mobileye/eyeq6h.dtsi

+4 −0
Original line number Diff line number Diff line
@@ -32,6 +32,10 @@ cpu_intc: interrupt-controller { 
		#interrupt-cells = <1>;

	};



	coherency-manager {

		compatible = "mobileye,eyeq6-cm";

	};



	xtal: clock-30000000 {

		compatible = "fixed-clock";

		#clock-cells = <0>;