Commit 1caf002e authored Dec 20, 2022 by Emil Renner Berthing Committed by Conor Dooley Dec 26, 2022

dt-bindings: sifive,ccache0: Support StarFive JH7110 SoC



This cache controller is also used on the StarFive JH7110 SoC.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

parent 1b929c02

Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml

+8 −1

Original line number	Diff line number	Diff line
		@@ -38,6 +38,10 @@ properties:
		- sifive,fu540-c000-ccache
		- sifive,fu740-c000-ccache
		- const: cache
		- items:
		- const: starfive,jh7110-ccache
		- const: sifive,ccache0
		- const: cache
		- items:
		- const: microchip,mpfs-ccache
		- const: sifive,fu540-c000-ccache
		@@ -85,6 +89,7 @@ allOf:
		contains:
		enum:
		- sifive,fu740-c000-ccache
		- starfive,jh7110-ccache
		- microchip,mpfs-ccache

		then:
		@@ -105,7 +110,9 @@ allOf:
		properties:
		compatible:
		contains:
		const: sifive,fu740-c000-ccache
		enum:
		- sifive,fu740-c000-ccache
		- starfive,jh7110-ccache

		then:
		properties: