Commit 1cb4db30 authored by Michal Wajdeczko's avatar Michal Wajdeczko
Browse files

drm/xe: Add helper to calculate adjusted register offset 



Our MMIO accessing functions automatically adjust addresses for the
media registers based on mmio.adj_limit and mmio.adj_offset logic.
Move it to the separate helper to avoid code duplication and to
allow using it by the upcoming changes to PF driver code.

Signed-off-by: default avatarMichal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Piotr Piórkowski <piotr.piorkowski@intel.com>
Reviewed-by: default avatarPiotr Piórkowski <piotr.piorkowski@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240423180436.2089-3-michal.wajdeczko@intel.com
parent 8f21f82d

drivers/gpu/drm/xe/xe_mmio.c

+15 −23
Original line number Diff line number Diff line
@@ -423,41 +423,33 @@ int xe_mmio_init(struct xe_device *xe) 
u8 xe_mmio_read8(struct xe_gt *gt, struct xe_reg reg)

{

	struct xe_tile *tile = gt_to_tile(gt);

	u32 addr = xe_mmio_adjusted_addr(gt, reg.addr);



	if (reg.addr < gt->mmio.adj_limit)

		reg.addr += gt->mmio.adj_offset;



	return readb((reg.ext ? tile->mmio_ext.regs : tile->mmio.regs) + reg.addr);

	return readb((reg.ext ? tile->mmio_ext.regs : tile->mmio.regs) + addr);

}



u16 xe_mmio_read16(struct xe_gt *gt, struct xe_reg reg)

{

	struct xe_tile *tile = gt_to_tile(gt);

	u32 addr = xe_mmio_adjusted_addr(gt, reg.addr);



	if (reg.addr < gt->mmio.adj_limit)

		reg.addr += gt->mmio.adj_offset;



	return readw((reg.ext ? tile->mmio_ext.regs : tile->mmio.regs) + reg.addr);

	return readw((reg.ext ? tile->mmio_ext.regs : tile->mmio.regs) + addr);

}



void xe_mmio_write32(struct xe_gt *gt, struct xe_reg reg, u32 val)

{

	struct xe_tile *tile = gt_to_tile(gt);

	u32 addr = xe_mmio_adjusted_addr(gt, reg.addr);



	if (reg.addr < gt->mmio.adj_limit)

		reg.addr += gt->mmio.adj_offset;



	writel(val, (reg.ext ? tile->mmio_ext.regs : tile->mmio.regs) + reg.addr);

	writel(val, (reg.ext ? tile->mmio_ext.regs : tile->mmio.regs) + addr);

}



u32 xe_mmio_read32(struct xe_gt *gt, struct xe_reg reg)

{

	struct xe_tile *tile = gt_to_tile(gt);

	u32 addr = xe_mmio_adjusted_addr(gt, reg.addr);



	if (reg.addr < gt->mmio.adj_limit)

		reg.addr += gt->mmio.adj_offset;



	return readl((reg.ext ? tile->mmio_ext.regs : tile->mmio.regs) + reg.addr);

	return readl((reg.ext ? tile->mmio_ext.regs : tile->mmio.regs) + addr);

}



u32 xe_mmio_rmw32(struct xe_gt *gt, struct xe_reg reg, u32 clr, u32 set)
@@ -486,10 +478,9 @@ bool xe_mmio_in_range(const struct xe_gt *gt, 
		      const struct xe_mmio_range *range,

		      struct xe_reg reg)

{

	if (reg.addr < gt->mmio.adj_limit)

		reg.addr += gt->mmio.adj_offset;

	u32 addr = xe_mmio_adjusted_addr(gt, reg.addr);



	return range && reg.addr >= range->start && reg.addr <= range->end;

	return range && addr >= range->start && addr <= range->end;

}



/**
@@ -519,10 +510,11 @@ u64 xe_mmio_read64_2x32(struct xe_gt *gt, struct xe_reg reg) 
	struct xe_reg reg_udw = { .addr = reg.addr + 0x4 };

	u32 ldw, udw, oldudw, retries;



	if (reg.addr < gt->mmio.adj_limit) {

		reg.addr += gt->mmio.adj_offset;

		reg_udw.addr += gt->mmio.adj_offset;

	}

	reg.addr = xe_mmio_adjusted_addr(gt, reg.addr);

	reg_udw.addr = xe_mmio_adjusted_addr(gt, reg_udw.addr);



	/* we shouldn't adjust just one register address */

	xe_gt_assert(gt, reg_udw.addr == reg.addr + 0x4);



	oldudw = xe_mmio_read32(gt, reg_udw);

	for (retries = 5; retries; --retries) {

drivers/gpu/drm/xe/xe_mmio.h

+7 −0
Original line number Diff line number Diff line
@@ -36,4 +36,11 @@ u64 xe_mmio_read64_2x32(struct xe_gt *gt, struct xe_reg reg); 
int xe_mmio_wait32(struct xe_gt *gt, struct xe_reg reg, u32 mask, u32 val, u32 timeout_us,

		   u32 *out_val, bool atomic);



static inline u32 xe_mmio_adjusted_addr(const struct xe_gt *gt, u32 addr)

{

	if (addr < gt->mmio.adj_limit)

		addr += gt->mmio.adj_offset;

	return addr;

}



#endif