Commit 1cbdfcfd authored by Théo Lebrun's avatar Théo Lebrun Committed by Stephen Boyd
Browse files

clk: eyeq: add EyeQ6H west fixed factor clocks 



Previous setup was:
 - pll-west clock registered from driver at of_clk_init();
 - Both OCC and UART clocks registered from DT using fixed-factor-clock
   compatible.

Now that drivers/clk/clk-eyeq.c supports registering fixed factors, use
that capability to register west-per-occ and west-per-uart (giving them
proper names at the same time).

Also switch from hard-coded index 0 for pll-west to using the
EQ6HC_WEST_PLL_PER constant by exposed dt-bindings headers.

All get exposed at of_clk_init() because they get used by the AMBA PL011
serial ports. Those are instantiated before platform bus infrastructure.

Signed-off-by: default avatarThéo Lebrun <theo.lebrun@bootlin.com>
Link: https://lore.kernel.org/r/20241106-mbly-clk-v2-8-84cfefb3f485@bootlin.com


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 0b28f9ee

drivers/clk/clk-eyeq.c

+9 −1
Original line number Diff line number Diff line
@@ -712,12 +712,20 @@ static const struct eqc_early_match_data eqc_eyeq6h_central_early_match_data __i 


/* Required early for UART. */

static const struct eqc_pll eqc_eyeq6h_west_early_plls[] = {

	{ .index = 0, .name = "pll-west", .reg64 = 0x074 },

	{ .index = EQ6HC_WEST_PLL_PER, .name = "pll-west", .reg64 = 0x074 },

};



static const struct eqc_fixed_factor eqc_eyeq6h_west_early_fixed_factors[] = {

	{ EQ6HC_WEST_PER_OCC,  "west-per-occ",  1, 10, EQ6HC_WEST_PLL_PER },

	{ EQ6HC_WEST_PER_UART, "west-per-uart", 1, 1,  EQ6HC_WEST_PER_OCC },

};



static const struct eqc_early_match_data eqc_eyeq6h_west_early_match_data __initconst = {

	.early_pll_count	= ARRAY_SIZE(eqc_eyeq6h_west_early_plls),

	.early_plls		= eqc_eyeq6h_west_early_plls,



	.early_fixed_factor_count = ARRAY_SIZE(eqc_eyeq6h_west_early_fixed_factors),

	.early_fixed_factors = eqc_eyeq6h_west_early_fixed_factors,

};



static void __init eqc_early_init(struct device_node *np,