Commit 1d00adb8 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-fixes-6.17-2025-09-10' of... 

Merge tag 'amd-drm-fixes-6.17-2025-09-10' of https://gitlab.freedesktop.org/agd5f/linux

 into drm-fixes

amd-drm-fixes-6.17-2025-09-10:

amdgpu:
- PSP 11.x fix
- DPCD quirk handing fix
- DCN 3.5 PG fix
- Audio suspend fix
- OEM i2c clean up fix
- Module unload memory leak fix
- DC delay fix
- ISP firmware fix
- VCN fixes

amdkfd:
- P2P topology fix
- APU mem limit calculation fix

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Alex Deucher <alexander.deucher@amd.com>
Link: https://lore.kernel.org/r/20250910162855.2507853-1-alexander.deucher@amd.com
parents 467360e2 3318f2d2

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

+32 −12
Original line number Diff line number Diff line
@@ -213,19 +213,35 @@ int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev, 
	spin_lock(&kfd_mem_limit.mem_limit_lock);



	if (kfd_mem_limit.system_mem_used + system_mem_needed >

	    kfd_mem_limit.max_system_mem_limit)

	    kfd_mem_limit.max_system_mem_limit) {

		pr_debug("Set no_system_mem_limit=1 if using shared memory\n");

		if (!no_system_mem_limit) {

			ret = -ENOMEM;

			goto release;

		}

	}



	if ((kfd_mem_limit.system_mem_used + system_mem_needed >

	     kfd_mem_limit.max_system_mem_limit && !no_system_mem_limit) ||

	    (kfd_mem_limit.ttm_mem_used + ttm_mem_needed >

	     kfd_mem_limit.max_ttm_mem_limit) ||

	    (adev && xcp_id >= 0 && adev->kfd.vram_used[xcp_id] + vram_needed >

	     vram_size - reserved_for_pt - reserved_for_ras - atomic64_read(&adev->vram_pin_size))) {

	if (kfd_mem_limit.ttm_mem_used + ttm_mem_needed >

		kfd_mem_limit.max_ttm_mem_limit) {

		ret = -ENOMEM;

		goto release;

	}



	/*if is_app_apu is false and apu_prefer_gtt is true, it is an APU with

	 * carve out < gtt. In that case, VRAM allocation will go to gtt domain, skip

	 * VRAM check since ttm_mem_limit check already cover this allocation

	 */



	if (adev && xcp_id >= 0 && (!adev->apu_prefer_gtt || adev->gmc.is_app_apu)) {

		uint64_t vram_available =

			vram_size - reserved_for_pt - reserved_for_ras -

			atomic64_read(&adev->vram_pin_size);

		if (adev->kfd.vram_used[xcp_id] + vram_needed > vram_available) {

			ret = -ENOMEM;

			goto release;

		}

	}



	/* Update memory accounting by decreasing available system

	 * memory, TTM memory and GPU memory as computed above

	 */
@@ -1626,6 +1642,10 @@ size_t amdgpu_amdkfd_get_available_memory(struct amdgpu_device *adev, 
	uint64_t vram_available, system_mem_available, ttm_mem_available;



	spin_lock(&kfd_mem_limit.mem_limit_lock);

	if (adev->apu_prefer_gtt && !adev->gmc.is_app_apu)

		vram_available = KFD_XCP_MEMORY_SIZE(adev, xcp_id)

			- adev->kfd.vram_used_aligned[xcp_id];

	else

		vram_available = KFD_XCP_MEMORY_SIZE(adev, xcp_id)

			- adev->kfd.vram_used_aligned[xcp_id]

			- atomic64_read(&adev->vram_pin_size)

drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c

+0 −2
Original line number Diff line number Diff line
@@ -421,8 +421,6 @@ void amdgpu_ring_fini(struct amdgpu_ring *ring) 
	dma_fence_put(ring->vmid_wait);

	ring->vmid_wait = NULL;

	ring->me = 0;



	ring->adev->rings[ring->idx] = NULL;

}



/**

drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.c

+2 −0
Original line number Diff line number Diff line
@@ -29,6 +29,8 @@ 
#include "amdgpu.h"

#include "isp_v4_1_1.h"



MODULE_FIRMWARE("amdgpu/isp_4_1_1.bin");



#define ISP_PERFORMANCE_STATE_LOW 0

#define ISP_PERFORMANCE_STATE_HIGH 1

drivers/gpu/drm/amd/amdgpu/psp_v11_0.c

+4 −15
Original line number Diff line number Diff line
@@ -149,12 +149,12 @@ static int psp_v11_0_wait_for_bootloader(struct psp_context *psp) 
	int ret;

	int retry_loop;



	for (retry_loop = 0; retry_loop < 10; retry_loop++) {

	for (retry_loop = 0; retry_loop < 20; retry_loop++) {

		/* Wait for bootloader to signify that is

		    ready having bit 31 of C2PMSG_35 set to 1 */

		ret = psp_wait_for(

			psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),

			0x80000000, 0x80000000, PSP_WAITREG_NOVERBOSE);

			0x80000000, 0x8000FFFF, PSP_WAITREG_NOVERBOSE);



		if (ret == 0)

			return 0;
@@ -397,18 +397,6 @@ static int psp_v11_0_mode1_reset(struct psp_context *psp) 


	msleep(500);



	offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);



	ret = psp_wait_for(psp, offset, MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK,

			   0);



	if (ret) {

		DRM_INFO("psp mode 1 reset failed!\n");

		return -EINVAL;

	}



	DRM_INFO("psp mode1 reset succeed \n");



	return 0;

}
@@ -665,7 +653,8 @@ static const struct psp_funcs psp_v11_0_funcs = { 
	.ring_get_wptr = psp_v11_0_ring_get_wptr,

	.ring_set_wptr = psp_v11_0_ring_set_wptr,

	.load_usbc_pd_fw = psp_v11_0_load_usbc_pd_fw,

	.read_usbc_pd_fw = psp_v11_0_read_usbc_pd_fw

	.read_usbc_pd_fw = psp_v11_0_read_usbc_pd_fw,

	.wait_for_bootloader = psp_v11_0_wait_for_bootloader

};



void psp_v11_0_set_psp_funcs(struct psp_context *psp)

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

+8 −4
Original line number Diff line number Diff line
@@ -1888,15 +1888,19 @@ static int vcn_v3_0_limit_sched(struct amdgpu_cs_parser *p, 
				struct amdgpu_job *job)

{

	struct drm_gpu_scheduler **scheds;



	/* The create msg must be in the first IB submitted */

	if (atomic_read(&job->base.entity->fence_seq))

		return -EINVAL;

	struct dma_fence *fence;



	/* if VCN0 is harvested, we can't support AV1 */

	if (p->adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0)

		return -EINVAL;



	/* wait for all jobs to finish before switching to instance 0 */

	fence = amdgpu_ctx_get_fence(p->ctx, job->base.entity, ~0ull);

	if (fence) {

		dma_fence_wait(fence, false);

		dma_fence_put(fence);

	}



	scheds = p->adev->gpu_sched[AMDGPU_HW_IP_VCN_DEC]

		[AMDGPU_RING_PRIO_DEFAULT].sched;

	drm_sched_entity_modify_sched(job->base.entity, scheds, 1);