Commit 1d26c846 authored by Jocelyn Falempe's avatar Jocelyn Falempe
Browse files

drm/nouveau: Add drm_panic support for nv50+ 



Add drm_panic support for nv50+ cards.
It's enough to get the panic screen while running Gnome/Wayland with
an nv50+ nvidia GPU.
It doesn't support multi-plane or compressed format yet.
Tiling is tested on GTX1650 (Turing), GeForce GT 1030 (Pascal) and
Geforce 8800 GTS (Tesla).

Signed-off-by: default avatarJocelyn Falempe <jfalempe@redhat.com>
Reviewed-by: default avatarLyude Paul <lyude@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241022185553.1103384-4-jfalempe@redhat.com
parent 74cfa1ef

drivers/gpu/drm/nouveau/dispnv50/wndw.c

+127 −2
Original line number Diff line number Diff line
@@ -30,14 +30,20 @@ 
#include <nvhw/class/cl507e.h>

#include <nvhw/class/clc37e.h>



#include <linux/iosys-map.h>



#include <drm/drm_atomic.h>

#include <drm/drm_atomic_helper.h>

#include <drm/drm_blend.h>

#include <drm/drm_gem_atomic_helper.h>

#include <drm/drm_fourcc.h>

#include <drm/drm_framebuffer.h>

#include <drm/drm_gem_atomic_helper.h>

#include <drm/drm_panic.h>

#include <drm/ttm/ttm_bo.h>



#include "nouveau_bo.h"

#include "nouveau_gem.h"

#include "tile.h"



static void

nv50_wndw_ctxdma_del(struct nv50_wndw_ctxdma *ctxdma)
@@ -577,6 +583,114 @@ nv50_wndw_prepare_fb(struct drm_plane *plane, struct drm_plane_state *state) 
	return 0;

}



/* Only used by drm_panic get_scanout_buffer() and set_pixel(), so it is

 * protected by the drm panic spinlock

 */

static u32 nv50_panic_blk_h;



/* Return the framebuffer offset of the start of the block where pixel(x,y) is */

static u32

nv50_get_block_off(unsigned int x, unsigned int y, unsigned int pitch)

{

	u32 blk_x, blk_y, blk_columns;



	blk_columns = nouveau_get_width_in_blocks(pitch);

	blk_x = (x * 4) / NV_TILE_GOB_WIDTH_BYTES;

	blk_y = y / nv50_panic_blk_h;



	return ((blk_y * blk_columns) + blk_x) * NV_TILE_GOB_WIDTH_BYTES * nv50_panic_blk_h;

}



/* Turing and later have 2 level of tiles inside the block */

static void

nv50_set_pixel_swizzle(struct drm_scanout_buffer *sb, unsigned int x,

		       unsigned int y, u32 color)

{

	u32 blk_off, off, swizzle;



	blk_off = nv50_get_block_off(x, y, sb->pitch[0]);



	y = y % nv50_panic_blk_h;



	/* Inside the block, use the fast address swizzle to compute the offset

	 * For nvidia blocklinear, bit order is yn..y3 x3 y2 x2 y1 y0 x1 x0

	 */

	swizzle = (x & 3) | (y & 3) << 2 | (x & 4) << 2 | (y & 4) << 3;

	swizzle |= (x & 8) << 3 | (y >> 3) << 7;

	off = blk_off + swizzle * 4;



	iosys_map_wr(&sb->map[0], off, u32, color);

}



static void

nv50_set_pixel(struct drm_scanout_buffer *sb, unsigned int x, unsigned int y,

	       u32 color)

{

	u32 blk_off, off;



	blk_off = nv50_get_block_off(x, y, sb->width);



	x = x % (NV_TILE_GOB_WIDTH_BYTES / 4);

	y = y % nv50_panic_blk_h;

	off = blk_off + x * 4 + y * NV_TILE_GOB_WIDTH_BYTES;



	iosys_map_wr(&sb->map[0], off, u32, color);

}



static int

nv50_wndw_get_scanout_buffer(struct drm_plane *plane, struct drm_scanout_buffer *sb)

{

	struct drm_framebuffer *fb;

	struct nouveau_bo *nvbo;

	struct nouveau_drm *drm = nouveau_drm(plane->dev);

	u16 chipset = drm->client.device.info.chipset;

	u8 family = drm->client.device.info.family;

	u32 tile_mode;

	u8 kind;



	if (!plane->state || !plane->state->fb)

		return -EINVAL;



	fb = plane->state->fb;

	nvbo = nouveau_gem_object(fb->obj[0]);



	/* Don't support compressed format, or multiplane yet. */

	if (nvbo->comp || fb->format->num_planes != 1)

		return -EOPNOTSUPP;



	if (nouveau_bo_map(nvbo)) {

		drm_warn(plane->dev, "nouveau bo map failed, panic won't be displayed\n");

		return -ENOMEM;

	}



	if (nvbo->kmap.bo_kmap_type & TTM_BO_MAP_IOMEM_MASK)

		iosys_map_set_vaddr_iomem(&sb->map[0], (void __iomem *)nvbo->kmap.virtual);

	else

		iosys_map_set_vaddr(&sb->map[0], nvbo->kmap.virtual);



	sb->height = fb->height;

	sb->width = fb->width;

	sb->pitch[0] = fb->pitches[0];

	sb->format = fb->format;



	nouveau_framebuffer_get_layout(fb, &tile_mode, &kind);

	if (kind) {

		/* If tiling is enabled, use set_pixel() to display correctly.

		 * Only handle 32bits format for now.

		 */

		if (fb->format->cpp[0] != 4)

			return -EOPNOTSUPP;

		nv50_panic_blk_h = nouveau_get_gob_height(family) *

				   nouveau_get_gobs_in_block(tile_mode, chipset);



		if (chipset >= 0x160)

			sb->set_pixel = nv50_set_pixel_swizzle;

		else

			sb->set_pixel = nv50_set_pixel;

	}

	return 0;

}



static const struct drm_plane_helper_funcs

nv50_wndw_helper = {

	.prepare_fb = nv50_wndw_prepare_fb,
@@ -584,6 +698,14 @@ nv50_wndw_helper = { 
	.atomic_check = nv50_wndw_atomic_check,

};



static const struct drm_plane_helper_funcs

nv50_wndw_primary_helper = {

	.prepare_fb = nv50_wndw_prepare_fb,

	.cleanup_fb = nv50_wndw_cleanup_fb,

	.atomic_check = nv50_wndw_atomic_check,

	.get_scanout_buffer = nv50_wndw_get_scanout_buffer,

};



static void

nv50_wndw_atomic_destroy_state(struct drm_plane *plane,

			       struct drm_plane_state *state)
@@ -732,6 +854,9 @@ nv50_wndw_new_(const struct nv50_wndw_func *func, struct drm_device *dev, 
		return ret;

	}



	if (type == DRM_PLANE_TYPE_PRIMARY)

		drm_plane_helper_add(&wndw->plane, &nv50_wndw_primary_helper);

	else

		drm_plane_helper_add(&wndw->plane, &nv50_wndw_helper);



	if (wndw->func->ilut) {