Unverified Commit 1d562ba0 authored by Tomer Maimon's avatar Tomer Maimon Committed by Mark Brown
Browse files

spi: dt-bindings: nuvoton,npcm-pspi: Convert to DT schema 



Convert the Nuvoton NPCM PSPI binding to DT schema format.

Also update the binding to fix shortcoming:
 * Drop clock-frequency property: it is never read in the NPCM PSPI
   driver and has no effect.

Signed-off-by: default avatarTomer Maimon <tmaimon77@gmail.com>
Reviewed-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://patch.msgid.link/20251112150950.1680154-1-tmaimon77@gmail.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 4a58f60d

Documentation/devicetree/bindings/spi/nuvoton,npcm-pspi.txt

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Nuvoton NPCM Peripheral Serial Peripheral Interface(PSPI) controller driver



Nuvoton NPCM7xx SOC support two PSPI channels.



Required properties:

 - compatible : "nuvoton,npcm750-pspi" for Poleg NPCM7XX.

				"nuvoton,npcm845-pspi" for Arbel NPCM8XX.

 - #address-cells : should be 1. see spi-bus.txt

 - #size-cells : should be 0. see spi-bus.txt

 - specifies physical base address and size of the register.

 - interrupts : contain PSPI interrupt.

 - clocks : phandle of PSPI reference clock.

 - clock-names: Should be "clk_apb5".

 - pinctrl-names : a pinctrl state named "default" must be defined.

 - pinctrl-0 : phandle referencing pin configuration of the device.

 - resets : phandle to the reset control for this device.

 - cs-gpios: Specifies the gpio pins to be used for chipselects.

            See: Documentation/devicetree/bindings/spi/spi-bus.txt



Optional properties:

- clock-frequency : Input clock frequency to the PSPI block in Hz.

		    Default is 25000000 Hz.



spi0: spi@f0200000 {

	compatible = "nuvoton,npcm750-pspi";

	reg = <0xf0200000 0x1000>;

	pinctrl-names = "default";

	pinctrl-0 = <&pspi1_pins>;

	#address-cells = <1>;

	#size-cells = <0>;

	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;

	clocks = <&clk NPCM7XX_CLK_APB5>;

	clock-names = "clk_apb5";

	resets = <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_PSPI1>

	cs-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;

};

Documentation/devicetree/bindings/spi/nuvoton,npcm-pspi.yaml

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/spi/nuvoton,npcm-pspi.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Nuvoton NPCM Peripheral SPI (PSPI) Controller



maintainers:

  - Tomer Maimon <tmaimon77@gmail.com>



allOf:

  - $ref: spi-controller.yaml#



description:

  Nuvoton NPCM Peripheral Serial Peripheral Interface (PSPI) controller.

  Nuvoton NPCM7xx SOC supports two PSPI channels.

  Nuvoton NPCM8xx SOC support one PSPI channel.



properties:

  compatible:

    enum:

      - nuvoton,npcm750-pspi # Poleg NPCM7XX

      - nuvoton,npcm845-pspi # Arbel NPCM8XX



  reg:

    maxItems: 1



  interrupts:

    maxItems: 1



  clocks:

    maxItems: 1

    description: PSPI reference clock.



  clock-names:

    items:

      - const: clk_apb5



  resets:

    maxItems: 1



required:

  - compatible

  - reg

  - interrupts

  - clocks

  - clock-names

  - resets



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/nuvoton,npcm7xx-clock.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/reset/nuvoton,npcm7xx-reset.h>

    #include "dt-bindings/gpio/gpio.h"

    spi0: spi@f0200000 {

        compatible = "nuvoton,npcm750-pspi";

        reg = <0xf0200000 0x1000>;

        pinctrl-names = "default";

        pinctrl-0 = <&pspi1_pins>;

        #address-cells = <1>;

        #size-cells = <0>;

        interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;

        clocks = <&clk NPCM7XX_CLK_APB5>;

        clock-names = "clk_apb5";

        resets = <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_PSPI1>;

        cs-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;

    };