Commit 1d9e6bc9 authored by Gustavo Sousa's avatar Gustavo Sousa Committed by Matt Roper
Browse files

drm/i915/xelpmp: Add Wa_16021867713 



This workaround applies to all steppings of Xe_LPM+. Implement the KMD
part.

v2:
    - Put the definition of VDBOX_CGCTL3F1C() in the correct sort order.
      (Matt)

Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Signed-off-by: default avatarGustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231106201959.156943-1-gustavo.sousa@intel.com
parent 34df0a03

drivers/gpu/drm/i915/gt/intel_engine_regs.h

+2 −0
Original line number Diff line number Diff line
@@ -263,5 +263,7 @@ 
#define VDBOX_CGCTL3F18(base)			_MMIO((base) + 0x3f18)

#define   ALNUNIT_CLKGATE_DIS			REG_BIT(13)



#define VDBOX_CGCTL3F1C(base)			_MMIO((base) + 0x3f1c)

#define   MFXPIPE_CLKGATE_DIS			REG_BIT(3)



#endif /* __INTEL_ENGINE_REGS__ */

drivers/gpu/drm/i915/gt/intel_workarounds.c

+14 −0
Original line number Diff line number Diff line
@@ -1662,9 +1662,23 @@ xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 
	debug_dump_steering(gt);

}



static void

wa_16021867713(struct intel_gt *gt, struct i915_wa_list *wal)

{

	struct intel_engine_cs *engine;

	int id;



	for_each_engine(engine, gt, id)

		if (engine->class == VIDEO_DECODE_CLASS)

			wa_write_or(wal, VDBOX_CGCTL3F1C(engine->mmio_base),

				    MFXPIPE_CLKGATE_DIS);

}



static void

xelpmp_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)

{

	wa_16021867713(gt, wal);



	/*

	 * Wa_14018778641

	 * Wa_18018781329