Merge tag 'amd-drm-next-6.11-2024-06-07' of...

.. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c

   :doc: pp_power_profile_mode

pm_policy

---------------------

.. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c

   :doc: pm_policy

\*_busy_percent

---------------

	select HWMON

	select I2C

	select I2C_ALGOBIT

	select CRC16

	select BACKLIGHT_CLASS_DEVICE

	select INTERVAL_TREE

	select DRM_BUDDY

amdgpu-y += \

	vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o vega10_reg_init.o \

	vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o arct_reg_init.o mxgpu_nv.o \

	nbio_v7_2.o hdp_v4_0.o hdp_v5_0.o aldebaran_reg_init.o aldebaran.o soc21.o \

	nbio_v7_2.o hdp_v4_0.o hdp_v5_0.o aldebaran_reg_init.o aldebaran.o soc21.o soc24.o \

	sienna_cichlid.o smu_v13_0_10.o nbio_v4_3.o hdp_v6_0.o nbio_v7_7.o hdp_v5_2.o lsdma_v6_0.o \

	nbio_v7_9.o aqua_vanjaram.o nbio_v7_11.o lsdma_v7_0.o hdp_v7_0.o nbif_v6_3_1.o

	gfxhub_v2_0.o mmhub_v2_0.o gmc_v10_0.o gfxhub_v2_1.o mmhub_v2_3.o \

	mmhub_v1_7.o gfxhub_v3_0.o mmhub_v3_0.o mmhub_v3_0_2.o gmc_v11_0.o \

	mmhub_v3_0_1.o gfxhub_v3_0_3.o gfxhub_v1_2.o mmhub_v1_8.o mmhub_v3_3.o \

	gfxhub_v11_5_0.o

	gfxhub_v11_5_0.o mmhub_v4_1_0.o gfxhub_v12_0.o gmc_v12_0.o

# add UMC block

amdgpu-y += \

	imu_v11_0.o \

	gfx_v11_0.o \

	gfx_v11_0_3.o \

	imu_v11_0_3.o

	imu_v11_0_3.o \

	gfx_v12_0.o \

	imu_v12_0.o

# add async DMA block

amdgpu-y += \

	sdma_v4_4_2.o \

	sdma_v5_0.o \

	sdma_v5_2.o \

	sdma_v6_0.o

	sdma_v6_0.o \

	sdma_v7_0.o

# add MES block

amdgpu-y += \

	amdgpu_mes.o \

	mes_v10_1.o \

	mes_v11_0.o

	mes_v11_0.o \

	mes_v12_0.o

# add UVD block

amdgpu-y += \

	amdgpu_amdkfd_gc_9_4_3.o \

	amdgpu_amdkfd_gfx_v10.o \

	amdgpu_amdkfd_gfx_v10_3.o \

	amdgpu_amdkfd_gfx_v11.o

	amdgpu_amdkfd_gfx_v11.o \

	amdgpu_amdkfd_gfx_v12.o

ifneq ($(CONFIG_DRM_AMDGPU_CIK),)

amdgpu-y += amdgpu_amdkfd_gfx_v7.o

extern int amdgpu_mes;

extern int amdgpu_mes_log_enable;

extern int amdgpu_mes_kiq;

extern int amdgpu_uni_mes;

extern int amdgpu_jpeg_test;

extern int amdgpu_noretry;

extern int amdgpu_force_asic_type;

extern int amdgpu_smartshift_bias;

extern int amdgpu_num_kcq;

#define AMDGPU_VCNFW_LOG_SIZE (32 * 1024)

#define AMDGPU_UMSCHFW_LOG_SIZE (32 * 1024)

extern int amdgpu_vcnfw_log;

extern int amdgpu_sg_display;

extern int amdgpu_umsch_mm;

extern int amdgpu_seamless;

extern int amdgpu_umsch_mm_fwlog;

extern int amdgpu_user_partt_mode;

extern int amdgpu_agp;

	AMDGPU_CP_KIQ_IRQ_LAST

};

#define SRIOV_USEC_TIMEOUT 1200000 /* wait 12 * 100ms for SRIOV */

#define MAX_KIQ_REG_WAIT       5000 /* in usecs, 5ms */

#define MAX_KIQ_REG_WAIT (amdgpu_sriov_vf(adev) ? 50000 : 5000) /* in usecs, extend for VF */

#define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */

#define MAX_KIQ_REG_TRY 1000

	/* jpeg */

	struct amdgpu_jpeg		jpeg;

	bool enable_jpeg_test;

	/* vpe */

	struct amdgpu_vpe		vpe;

	/* mes */

	bool                            enable_mes;

	bool                            enable_mes_kiq;

	bool                            enable_uni_mes;

	struct amdgpu_mes               mes;

	struct amdgpu_mqd               mqds[AMDGPU_HW_IP_NUM];

	bool                            debug_largebar;

	bool                            debug_disable_soft_recovery;

	bool                            debug_use_vram_fw_buf;

	bool                            debug_enable_ras_aca;

};

static inline uint32_t amdgpu_ip_version(const struct amdgpu_device *adev,

	INIT_LIST_HEAD(&bank_error->node);

	memcpy(&bank_error->info, info, sizeof(*info));

	mutex_lock(&aerr->lock);

	spin_lock(&aerr->lock);

	list_add_tail(&bank_error->node, &aerr->list);

	mutex_unlock(&aerr->lock);

	spin_unlock(&aerr->lock);

	return bank_error;

}

	struct aca_bank_info *tmp_info;

	bool found = false;

	mutex_lock(&aerr->lock);

	spin_lock(&aerr->lock);

	list_for_each_entry(bank_error, &aerr->list, node) {

		tmp_info = &bank_error->info;

		if (tmp_info->socket_id == info->socket_id &&

	}

out_unlock:

	mutex_unlock(&aerr->lock);

	spin_unlock(&aerr->lock);

	return found ? bank_error : NULL;

}

	struct aca_error *aerr = &error_cache->errors[type];

	struct aca_bank_error *bank_error, *tmp;

	mutex_lock(&aerr->lock);

	spin_lock(&aerr->lock);

	if (list_empty(&aerr->list))

		goto out_unlock;

	}

out_unlock:

	mutex_unlock(&aerr->lock);

	spin_unlock(&aerr->lock);

	return 0;

}

	if (aca_handle_is_valid(handle))

		return -EOPNOTSUPP;

	if (!(BIT(type) & handle->mask))

	if ((type < 0) || (!(BIT(type) & handle->mask)))

		return  0;

	return __aca_get_error_data(adev, handle, type, err_data, qctx);

static void aca_error_init(struct aca_error *aerr, enum aca_error_type type)

{

	mutex_init(&aerr->lock);

	spin_lock_init(&aerr->lock);

	INIT_LIST_HEAD(&aerr->list);

	aerr->type = type;

	aerr->nr_errors = 0;

{

	struct aca_bank_error *bank_error, *tmp;

	mutex_lock(&aerr->lock);

	spin_lock(&aerr->lock);

	list_for_each_entry_safe(bank_error, tmp, &aerr->list, node)

		aca_bank_error_remove(aerr, bank_error);

	mutex_destroy(&aerr->lock);

	spin_unlock(&aerr->lock);

}

static void aca_fini_error_cache(struct aca_handle *handle)

bool amdgpu_aca_is_enabled(struct amdgpu_device *adev)

{

	return adev->aca.is_enabled;

	return (adev->aca.is_enabled ||

		adev->debug_enable_ras_aca);

}

int amdgpu_aca_init(struct amdgpu_device *adev)

	atomic_set(&aca->ue_update_flag, 0);

}

int amdgpu_aca_reset(struct amdgpu_device *adev)

{

	amdgpu_aca_fini(adev);

	return amdgpu_aca_init(adev);

}

void amdgpu_aca_set_smu_funcs(struct amdgpu_device *adev, const struct aca_smu_funcs *smu_funcs)

{

	struct amdgpu_aca *aca = &adev->aca;

void amdgpu_aca_smu_debugfs_init(struct amdgpu_device *adev, struct dentry *root)

{

#if defined(CONFIG_DEBUG_FS)

	if (!root || adev->ip_versions[MP1_HWIP][0] != IP_VERSION(13, 0, 6))

	if (!root ||

	    (adev->ip_versions[MP1_HWIP][0] != IP_VERSION(13, 0, 6) &&

	     adev->ip_versions[MP1_HWIP][0] != IP_VERSION(13, 0, 14)))

		return;

	debugfs_create_file("aca_debug_mode", 0200, root, adev, &aca_debug_mode_fops);