Commit 1e66d6cf authored by Tony Luck's avatar Tony Luck Committed by Dave Hansen
Browse files

x86/cpu: Fix #define name for Intel CPU model 0x5A 



This CPU was mistakenly given the name INTEL_ATOM_AIRMONT_MID. But it
uses a Silvermont core, not Airmont.

Change #define name to INTEL_ATOM_SILVERMONT_MID2

Reported-by: default avatarChristian Ludloff <ludloff@gmail.com>
Signed-off-by: default avatarTony Luck <tony.luck@intel.com>
Signed-off-by: default avatarDave Hansen <dave.hansen@linux.intel.com>
Link: https://lore.kernel.org/all/20241007165701.19693-1-tony.luck%40intel.com
parent 2014c95a

arch/x86/events/intel/core.c

+1 −1
Original line number Diff line number Diff line
@@ -6622,7 +6622,7 @@ __init int intel_pmu_init(void) 
	case INTEL_ATOM_SILVERMONT_D:

	case INTEL_ATOM_SILVERMONT_MID:

	case INTEL_ATOM_AIRMONT:

	case INTEL_ATOM_AIRMONT_MID:

	case INTEL_ATOM_SILVERMONT_MID2:

		memcpy(hw_cache_event_ids, slm_hw_cache_event_ids,

			sizeof(hw_cache_event_ids));

		memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs,

arch/x86/include/asm/intel-family.h

+1 −1
Original line number Diff line number Diff line
@@ -149,9 +149,9 @@ 
#define INTEL_ATOM_SILVERMONT		IFM(6, 0x37) /* Bay Trail, Valleyview */

#define INTEL_ATOM_SILVERMONT_D		IFM(6, 0x4D) /* Avaton, Rangely */

#define INTEL_ATOM_SILVERMONT_MID	IFM(6, 0x4A) /* Merriefield */

#define INTEL_ATOM_SILVERMONT_MID2	IFM(6, 0x5A) /* Anniedale */



#define INTEL_ATOM_AIRMONT		IFM(6, 0x4C) /* Cherry Trail, Braswell */

#define INTEL_ATOM_AIRMONT_MID		IFM(6, 0x5A) /* Moorefield */

#define INTEL_ATOM_AIRMONT_NP		IFM(6, 0x75) /* Lightning Mountain */



#define INTEL_ATOM_GOLDMONT		IFM(6, 0x5C) /* Apollo Lake */

arch/x86/kernel/cpu/common.c

+1 −1
Original line number Diff line number Diff line
@@ -1164,7 +1164,7 @@ static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = { 


	VULNWL_INTEL(INTEL_CORE_YONAH,		NO_SSB),



	VULNWL_INTEL(INTEL_ATOM_AIRMONT_MID,	NO_SSB | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | MSBDS_ONLY),

	VULNWL_INTEL(INTEL_ATOM_SILVERMONT_MID2,NO_SSB | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | MSBDS_ONLY),

	VULNWL_INTEL(INTEL_ATOM_AIRMONT_NP,	NO_SSB | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT),



	VULNWL_INTEL(INTEL_ATOM_GOLDMONT,	NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),

arch/x86/kernel/tsc_msr.c

+1 −1
Original line number Diff line number Diff line
@@ -152,7 +152,7 @@ static const struct x86_cpu_id tsc_msr_cpu_ids[] = { 
	X86_MATCH_VFM(INTEL_ATOM_SILVERMONT,	&freq_desc_byt),

	X86_MATCH_VFM(INTEL_ATOM_SILVERMONT_MID,	&freq_desc_tng),

	X86_MATCH_VFM(INTEL_ATOM_AIRMONT,	&freq_desc_cht),

	X86_MATCH_VFM(INTEL_ATOM_AIRMONT_MID,	&freq_desc_ann),

	X86_MATCH_VFM(INTEL_ATOM_SILVERMONT_MID2,	&freq_desc_ann),

	X86_MATCH_VFM(INTEL_ATOM_AIRMONT_NP,	&freq_desc_lgm),

	{}

};

drivers/powercap/intel_rapl_common.c

+1 −1
Original line number Diff line number Diff line
@@ -1274,7 +1274,7 @@ static const struct x86_cpu_id rapl_ids[] __initconst = { 
	X86_MATCH_VFM(INTEL_ATOM_SILVERMONT,	&rapl_defaults_byt),

	X86_MATCH_VFM(INTEL_ATOM_AIRMONT,	&rapl_defaults_cht),

	X86_MATCH_VFM(INTEL_ATOM_SILVERMONT_MID, &rapl_defaults_tng),

	X86_MATCH_VFM(INTEL_ATOM_AIRMONT_MID,	&rapl_defaults_ann),

	X86_MATCH_VFM(INTEL_ATOM_SILVERMONT_MID2,&rapl_defaults_ann),

	X86_MATCH_VFM(INTEL_ATOM_GOLDMONT,	&rapl_defaults_core),

	X86_MATCH_VFM(INTEL_ATOM_GOLDMONT_PLUS,	&rapl_defaults_core),

	X86_MATCH_VFM(INTEL_ATOM_GOLDMONT_D,	&rapl_defaults_core),