Commit 1f5df537 authored by Jouni Högander's avatar Jouni Högander
Browse files

drm/i915/psr: Set plane id bit in crtc_state->async_flip_planes for PSR 



Currently plane id bit is set in crtc_state->async_flip_planes only when
async flip toggle workaround is needed. We want to utilize
crtc_state->async_flip_planes further in Selective Fetch calculation.

v2:
  - rework if-else if to if-if
  - added comment updated

Signed-off-by: default avatarJouni Högander <jouni.hogander@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patch.msgid.link/20251204070718.1090778-2-jouni.hogander@intel.com
parent 0c085485

drivers/gpu/drm/i915/display/intel_plane.c

+6 −4
Original line number Diff line number Diff line
@@ -655,11 +655,10 @@ static int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_cr 
	    ilk_must_disable_cxsr(new_crtc_state, old_plane_state, new_plane_state))

		new_crtc_state->disable_cxsr = true;



	if (intel_plane_do_async_flip(plane, old_crtc_state, new_crtc_state)) {

	if (intel_plane_do_async_flip(plane, old_crtc_state, new_crtc_state))

		new_crtc_state->do_async_flip = true;

		new_crtc_state->async_flip_planes |= BIT(plane->id);

	} else if (plane->need_async_flip_toggle_wa &&

		   new_crtc_state->uapi.async_flip) {



	if (new_crtc_state->uapi.async_flip) {

		/*

		 * On platforms with double buffered async flip bit we

		 * set the bit already one frame early during the sync
@@ -667,6 +666,9 @@ static int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_cr 
		 * hardware will therefore be ready to perform a real

		 * async flip during the next commit, without having

		 * to wait yet another frame for the bit to latch.

		 *

		 * async_flip_planes bitmask is also used by selective

		 * fetch calculation to choose full frame update.

		 */

		new_crtc_state->async_flip_planes |= BIT(plane->id);

	}