Commit 1fa3ed04 authored by Sudeep Holla's avatar Sudeep Holla
Browse files

arm64: dts: arm: Drop the clock-frequency property from timer nodes 



Drop the clock-frequency property from the timer nodes, since it must be
configured by the boot/secure firmware.

Cc: Liviu Dudau <liviu.dudau@arm.com>
Cc: Lorenzo Pieralisi <lpieralisi@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Message-Id: <20250512101132.1743920-1-sudeep.holla@arm.com>
Signed-off-by: default avatarSudeep Holla <sudeep.holla@arm.com>
parent bbb59b36

arch/arm64/boot/dts/arm/corstone1000.dtsi

+0 −1
Original line number Diff line number Diff line
@@ -109,7 +109,6 @@ timer@1a220000 { 
			reg = <0x1a220000 0x1000>;

			#address-cells = <1>;

			#size-cells = <1>;

			clock-frequency = <50000000>;

			ranges;



			frame@1a230000 {

arch/arm64/boot/dts/arm/foundation-v8.dtsi

+0 −1
Original line number Diff line number Diff line
@@ -77,7 +77,6 @@ timer { 
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;

		clock-frequency = <100000000>;

	};



	pmu {

arch/arm64/boot/dts/arm/juno-base.dtsi

+0 −1
Original line number Diff line number Diff line
@@ -10,7 +10,6 @@ / { 
	memtimer: timer@2a810000 {

		compatible = "arm,armv7-timer-mem";

		reg = <0x0 0x2a810000 0x0 0x10000>;

		clock-frequency = <50000000>;

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0 0x0 0x2a820000 0x20000>;

arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts

+0 −1
Original line number Diff line number Diff line
@@ -116,7 +116,6 @@ timer { 
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;

		clock-frequency = <100000000>;

	};



	pmu {