Commit 208d8c79 authored by H. Peter Anvin (Intel)'s avatar H. Peter Anvin (Intel) Committed by Borislav Petkov (AMD)
Browse files

x86/fred: Invoke FRED initialization code to enable FRED 



Let cpu_init_exception_handling() call cpu_init_fred_exceptions() to
initialize FRED. However if FRED is unavailable or disabled, it falls
back to set up TSS IST and initialize IDT.

Co-developed-by: default avatarXin Li <xin3.li@intel.com>
Signed-off-by: default avatarH. Peter Anvin (Intel) <hpa@zytor.com>
Signed-off-by: default avatarXin Li <xin3.li@intel.com>
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Signed-off-by: default avatarBorislav Petkov (AMD) <bp@alien8.de>
Tested-by: default avatarShan Kang <shan.kang@intel.com>
Link: https://lore.kernel.org/r/20231205105030.8698-36-xin3.li@intel.com
parent cdd99dd8

arch/x86/kernel/cpu/common.c

+17 −5
Original line number Diff line number Diff line
@@ -61,6 +61,7 @@ 
#include <asm/microcode.h>

#include <asm/intel-family.h>

#include <asm/cpu_device_id.h>

#include <asm/fred.h>

#include <asm/uv/uv.h>

#include <asm/ia32.h>

#include <asm/set_memory.h>
@@ -2107,6 +2108,14 @@ void syscall_init(void) 
	/* The default user and kernel segments */

	wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS);



	/*

	 * Except the IA32_STAR MSR, there is NO need to setup SYSCALL and

	 * SYSENTER MSRs for FRED, because FRED uses the ring 3 FRED

	 * entrypoint for SYSCALL and SYSENTER, and ERETU is the only legit

	 * instruction to return to ring 3 (both sysexit and sysret cause

	 * #UD when FRED is enabled).

	 */

	if (!cpu_feature_enabled(X86_FEATURE_FRED))

		idt_syscall_init();

}
@@ -2213,7 +2222,8 @@ void cpu_init_exception_handling(void) 
	/* paranoid_entry() gets the CPU number from the GDT */

	setup_getcpu(cpu);



	/* IST vectors need TSS to be set up. */

	/* For IDT mode, IST vectors need to be set in TSS. */

	if (!cpu_feature_enabled(X86_FEATURE_FRED))

		tss_setup_ist(tss);

	tss_setup_io_bitmap(tss);

	set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss);
@@ -2223,7 +2233,9 @@ void cpu_init_exception_handling(void) 
	/* GHCB needs to be setup to handle #VC. */

	setup_ghcb();



	/* Finally load the IDT */

	if (cpu_feature_enabled(X86_FEATURE_FRED))

		cpu_init_fred_exceptions();

	else

		load_current_idt();

}

arch/x86/kernel/irqinit.c

+6 −1
Original line number Diff line number Diff line
@@ -28,6 +28,7 @@ 
#include <asm/setup.h>

#include <asm/i8259.h>

#include <asm/traps.h>

#include <asm/fred.h>

#include <asm/prom.h>



/*
@@ -96,7 +97,11 @@ void __init native_init_IRQ(void) 
	/* Execute any quirks before the call gates are initialised: */

	x86_init.irqs.pre_vector_init();



	if (cpu_feature_enabled(X86_FEATURE_FRED))

		fred_complete_exception_setup();

	else

		idt_setup_apic_and_irq_gates();



	lapic_assign_system_vectors();



	if (!acpi_ioapic && !of_ioapic && nr_legacy_irqs()) {

arch/x86/kernel/traps.c

+4 −1
Original line number Diff line number Diff line
@@ -1438,7 +1438,10 @@ void __init trap_init(void) 


	/* Initialize TSS before setting up traps so ISTs work */

	cpu_init_exception_handling();



	/* Setup traps as cpu_init() might #GP */

	if (!cpu_feature_enabled(X86_FEATURE_FRED))

		idt_setup_traps();



	cpu_init();

}