Unverified Commit 22a91204 authored by Siddharth Vadapalli's avatar Siddharth Vadapalli Committed by Krzysztof Wilczyński
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PCI: j721e: Deassert PERST# after a delay of PCIE_T_PVPERL_MS milliseconds 

According to Section 2.2 of the PCI Express Card Electromechanical
Specification (Revision 5.1), in order to ensure that the power and the
reference clock are stable, PERST# has to be deasserted after a delay of
100 milliseconds (TPVPERL).

Currently, it is being assumed that the power is already stable, which
is not necessarily true.

Hence, change the delay to PCIE_T_PVPERL_MS to guarantee that power and
reference clock are stable.

Fixes: f3e25911 ("PCI: j721e: Add TI J721E PCIe driver")
Fixes: f96b6971 ("PCI: j721e: Use T_PERST_CLK_US macro")
Link: https://lore.kernel.org/r/20241104074420.1862932-1-s-vadapalli@ti.com


Signed-off-by: default avatarSiddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: default avatarKrzysztof Wilczyński <kwilczynski@kernel.org>
parent 08e83526

drivers/pci/controller/cadence/pci-j721e.c

+12 −14
Original line number Diff line number Diff line
@@ -583,15 +583,14 @@ static int j721e_pcie_probe(struct platform_device *pdev) 
		pcie->refclk = clk;



		/*

		 * The "Power Sequencing and Reset Signal Timings" table of the

		 * PCI Express Card Electromechanical Specification, Revision

		 * 5.1, Section 2.9.2, Symbol "T_PERST-CLK", indicates PERST#

		 * should be deasserted after minimum of 100us once REFCLK is

		 * stable. The REFCLK to the connector in RC mode is selected

		 * while enabling the PHY. So deassert PERST# after 100 us.

		 * Section 2.2 of the PCI Express Card Electromechanical

		 * Specification (Revision 5.1) mandates that the deassertion

		 * of the PERST# signal should be delayed by 100 ms (TPVPERL).

		 * This shall ensure that the power and the reference clock

		 * are stable.

		 */

		if (gpiod) {

			fsleep(PCIE_T_PERST_CLK_US);

			msleep(PCIE_T_PVPERL_MS);

			gpiod_set_value_cansleep(gpiod, 1);

		}
@@ -682,15 +681,14 @@ static int j721e_pcie_resume_noirq(struct device *dev) 
			return ret;



		/*

		 * The "Power Sequencing and Reset Signal Timings" table of the

		 * PCI Express Card Electromechanical Specification, Revision

		 * 5.1, Section 2.9.2, Symbol "T_PERST-CLK", indicates PERST#

		 * should be deasserted after minimum of 100us once REFCLK is

		 * stable. The REFCLK to the connector in RC mode is selected

		 * while enabling the PHY. So deassert PERST# after 100 us.

		 * Section 2.2 of the PCI Express Card Electromechanical

		 * Specification (Revision 5.1) mandates that the deassertion

		 * of the PERST# signal should be delayed by 100 ms (TPVPERL).

		 * This shall ensure that the power and the reference clock

		 * are stable.

		 */

		if (pcie->reset_gpio) {

			fsleep(PCIE_T_PERST_CLK_US);

			msleep(PCIE_T_PVPERL_MS);

			gpiod_set_value_cansleep(pcie->reset_gpio, 1);

		}