Commit 22a9d5cb authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu/gfx9.4.3: implement wave kill for compute queues 



Based on gfx9.0 implementation.

Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent eac3b274

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

+14 −0
Original line number Diff line number Diff line
@@ -2833,6 +2833,19 @@ static void gfx_v9_4_3_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 
						   ref, mask);

}



static void gfx_v9_4_3_ring_soft_recovery(struct amdgpu_ring *ring,

					  unsigned vmid)

{

	struct amdgpu_device *adev = ring->adev;

	uint32_t value = 0;



	value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);

	value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);

	value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);

	value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);

	WREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regSQ_CMD, value);

}



static void gfx_v9_4_3_xcc_set_compute_eop_interrupt_state(

	struct amdgpu_device *adev, int me, int pipe,

	enum amdgpu_interrupt_state state, int xcc_id)
@@ -4116,6 +4129,7 @@ static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_compute = { 
	.emit_wreg = gfx_v9_4_3_ring_emit_wreg,

	.emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait,

	.emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait,

	.soft_recovery = gfx_v9_4_3_ring_soft_recovery,

	.emit_mem_sync = gfx_v9_4_3_emit_mem_sync,

	.emit_wave_limit = gfx_v9_4_3_emit_wave_limit,

};