Commit 23608993 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'locking-core-2025-03-22' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull locking updates from Ingo Molnar:
 "Locking primitives:
   - Micro-optimize percpu_{,try_}cmpxchg{64,128}_op() and
     {,try_}cmpxchg{64,128} on x86 (Uros Bizjak)
   - mutexes: extend debug checks in mutex_lock() (Yunhui Cui)
   - Misc cleanups (Uros Bizjak)

  Lockdep:
   - Fix might_fault() lockdep check of current->mm->mmap_lock (Peter
     Zijlstra)
   - Don't disable interrupts on RT in disable_irq_nosync_lockdep.*()
     (Sebastian Andrzej Siewior)
   - Disable KASAN instrumentation of lockdep.c (Waiman Long)
   - Add kasan_check_byte() check in lock_acquire() (Waiman Long)
   - Misc cleanups (Sebastian Andrzej Siewior)

  Rust runtime integration:
   - Use Pin for all LockClassKey usages (Mitchell Levy)
   - sync: Add accessor for the lock behind a given guard (Alice Ryhl)
   - sync: condvar: Add wait_interruptible_freezable() (Alice Ryhl)
   - sync: lock: Add an example for Guard:: Lock_ref() (Boqun Feng)

  Split-lock detection feature (x86):
   - Fix warning mode with disabled mitigation mode (Maksim Davydov)

  Locking events:
   - Add locking events for rtmutex slow paths (Waiman Long)
   - Add locking events for lockdep (Waiman Long)"

* tag 'locking-core-2025-03-22' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  lockdep: Remove disable_irq_lockdep()
  lockdep: Don't disable interrupts on RT in disable_irq_nosync_lockdep.*()
  rust: lockdep: Use Pin for all LockClassKey usages
  rust: sync: condvar: Add wait_interruptible_freezable()
  rust: sync: lock: Add an example for Guard:: Lock_ref()
  rust: sync: Add accessor for the lock behind a given guard
  locking/lockdep: Add kasan_check_byte() check in lock_acquire()
  locking/lockdep: Disable KASAN instrumentation of lockdep.c
  locking/lock_events: Add locking events for lockdep
  locking/lock_events: Add locking events for rtmutex slow paths
  x86/split_lock: Fix the delayed detection logic
  lockdep/mm: Fix might_fault() lockdep check of current->mm->mmap_lock
  x86/locking: Remove semicolon from "lock" prefix
  locking/mutex: Add MUTEX_WARN_ON() into fast path
  x86/locking: Use asm_inline for {,try_}cmpxchg{64,128} emulations
  x86/locking: Use ALT_OUTPUT_SP() for percpu_{,try_}cmpxchg{64,128}_op()
parents 3ba7dfb8 35e6b537

arch/x86/include/asm/alternative.h

+1 −1
Original line number Diff line number Diff line
@@ -48,7 +48,7 @@ 
		".popsection\n"				\

		"671:"



#define LOCK_PREFIX LOCK_PREFIX_HERE "\n\tlock; "

#define LOCK_PREFIX LOCK_PREFIX_HERE "\n\tlock "



#else /* ! CONFIG_SMP */

#define LOCK_PREFIX_HERE ""

arch/x86/include/asm/barrier.h

+4 −4
Original line number Diff line number Diff line
@@ -12,11 +12,11 @@ 
 */



#ifdef CONFIG_X86_32

#define mb() asm volatile(ALTERNATIVE("lock; addl $0,-4(%%esp)", "mfence", \

#define mb() asm volatile(ALTERNATIVE("lock addl $0,-4(%%esp)", "mfence", \

				      X86_FEATURE_XMM2) ::: "memory", "cc")

#define rmb() asm volatile(ALTERNATIVE("lock; addl $0,-4(%%esp)", "lfence", \

#define rmb() asm volatile(ALTERNATIVE("lock addl $0,-4(%%esp)", "lfence", \

				       X86_FEATURE_XMM2) ::: "memory", "cc")

#define wmb() asm volatile(ALTERNATIVE("lock; addl $0,-4(%%esp)", "sfence", \

#define wmb() asm volatile(ALTERNATIVE("lock addl $0,-4(%%esp)", "sfence", \

				       X86_FEATURE_XMM2) ::: "memory", "cc")

#else

#define __mb()	asm volatile("mfence":::"memory")
@@ -50,7 +50,7 @@ 
#define __dma_rmb()	barrier()

#define __dma_wmb()	barrier()



#define __smp_mb()	asm volatile("lock; addl $0,-4(%%" _ASM_SP ")" ::: "memory", "cc")

#define __smp_mb()	asm volatile("lock addl $0,-4(%%" _ASM_SP ")" ::: "memory", "cc")



#define __smp_rmb()	dma_rmb()

#define __smp_wmb()	barrier()

arch/x86/include/asm/cmpxchg.h

+2 −2
Original line number Diff line number Diff line
@@ -134,7 +134,7 @@ extern void __add_wrong_size(void) 
	__raw_cmpxchg((ptr), (old), (new), (size), LOCK_PREFIX)



#define __sync_cmpxchg(ptr, old, new, size)				\

	__raw_cmpxchg((ptr), (old), (new), (size), "lock; ")

	__raw_cmpxchg((ptr), (old), (new), (size), "lock ")



#define __cmpxchg_local(ptr, old, new, size)				\

	__raw_cmpxchg((ptr), (old), (new), (size), "")
@@ -222,7 +222,7 @@ extern void __add_wrong_size(void) 
	__raw_try_cmpxchg((ptr), (pold), (new), (size), LOCK_PREFIX)



#define __sync_try_cmpxchg(ptr, pold, new, size)			\

	__raw_try_cmpxchg((ptr), (pold), (new), (size), "lock; ")

	__raw_try_cmpxchg((ptr), (pold), (new), (size), "lock ")



#define __try_cmpxchg_local(ptr, pold, new, size)			\

	__raw_try_cmpxchg((ptr), (pold), (new), (size), "")

arch/x86/include/asm/cmpxchg_32.h

+20 −16
Original line number Diff line number Diff line
@@ -91,11 +91,13 @@ static __always_inline bool __try_cmpxchg64_local(volatile u64 *ptr, u64 *oldp, 
	union __u64_halves o = { .full = (_old), },			\

			   n = { .full = (_new), };			\

									\

	asm volatile(ALTERNATIVE(_lock_loc				\

	asm_inline volatile(						\

		ALTERNATIVE(_lock_loc					\

			    "call cmpxchg8b_emu",			\

			    _lock "cmpxchg8b %a[ptr]", X86_FEATURE_CX8)	\

		: ALT_OUTPUT_SP("+a" (o.low), "+d" (o.high))		\

		     : "b" (n.low), "c" (n.high), [ptr] "S" (_ptr)	\

		: "b" (n.low), "c" (n.high),				\

		  [ptr] "S" (_ptr)					\

		: "memory");						\

									\

	o.full;								\
@@ -103,7 +105,7 @@ static __always_inline bool __try_cmpxchg64_local(volatile u64 *ptr, u64 *oldp, 


static __always_inline u64 arch_cmpxchg64(volatile u64 *ptr, u64 old, u64 new)

{

	return __arch_cmpxchg64_emu(ptr, old, new, LOCK_PREFIX_HERE, "lock; ");

	return __arch_cmpxchg64_emu(ptr, old, new, LOCK_PREFIX_HERE, "lock ");

}

#define arch_cmpxchg64 arch_cmpxchg64
@@ -119,13 +121,15 @@ static __always_inline u64 arch_cmpxchg64_local(volatile u64 *ptr, u64 old, u64 
			   n = { .full = (_new), };			\

	bool ret;							\

									\

	asm volatile(ALTERNATIVE(_lock_loc				\

	asm_inline volatile(						\

		ALTERNATIVE(_lock_loc					\

			    "call cmpxchg8b_emu",			\

			    _lock "cmpxchg8b %a[ptr]", X86_FEATURE_CX8) \

		CC_SET(e)						\

		: ALT_OUTPUT_SP(CC_OUT(e) (ret),			\

				"+a" (o.low), "+d" (o.high))		\

		     : "b" (n.low), "c" (n.high), [ptr] "S" (_ptr)	\

		: "b" (n.low), "c" (n.high),				\

		  [ptr] "S" (_ptr)					\

		: "memory");						\

									\

	if (unlikely(!ret))						\
@@ -136,7 +140,7 @@ static __always_inline u64 arch_cmpxchg64_local(volatile u64 *ptr, u64 old, u64 


static __always_inline bool arch_try_cmpxchg64(volatile u64 *ptr, u64 *oldp, u64 new)

{

	return __arch_try_cmpxchg64_emu(ptr, oldp, new, LOCK_PREFIX_HERE, "lock; ");

	return __arch_try_cmpxchg64_emu(ptr, oldp, new, LOCK_PREFIX_HERE, "lock ");

}

#define arch_try_cmpxchg64 arch_try_cmpxchg64

arch/x86/include/asm/edac.h

+1 −1
Original line number Diff line number Diff line
@@ -13,7 +13,7 @@ static inline void edac_atomic_scrub(void *va, u32 size) 
	 * are interrupt, DMA and SMP safe.

	 */

	for (i = 0; i < size / 4; i++, virt_addr++)

		asm volatile("lock; addl $0, %0"::"m" (*virt_addr));

		asm volatile("lock addl $0, %0"::"m" (*virt_addr));

}



#endif /* _ASM_X86_EDAC_H */