Commit 236f475d authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-next-6.15-2025-03-07' of... 

Merge tag 'amd-drm-next-6.15-2025-03-07' of https://gitlab.freedesktop.org/agd5f/linux into drm-next

amdgpu:
- Fix spelling typos
- RAS updates
- VCN 5.0.1 updates
- SubVP fixes
- DCN 4.0.1 fixes
- MSO DPCD fixes
- DIO encoder refactor
- PCON fixes
- Misc cleanups
- DMCUB fixes
- USB4 DP fixes
- DM cleanups
- Backlight cleanups and fixes
- Support platform backlight curves
- Misc code cleanups
- SMU 14 fixes
- JPEG 4.0.3 reset updates
- SR-IOV fixes
- SVM fixes
- GC 12 DCC fixes
- DC DCE 6.x fix
- Hiberation fix

amdkfd:
- Fix possible NULL pointer in queue validation
- Remove unnecessary CP domain validation
- SDMA queue reset support
- Add per process flags

radeon:
- Fix spelling typos
- RS400 hyperZ fix

UAPI:
- Add KFD per process flags for setting precision
  Proposed user space: https://github.com/ROCm/ROCR-Runtime/commit/2a64fa5e06e80e0af36df4ce0c76ae52eeec0a9d



Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250307211051.1880472-1-alexander.deucher@amd.com
parents d65a27f9 cf6d949a

.mailmap

+2 −0
Original line number Diff line number Diff line
@@ -614,6 +614,8 @@ Richard Leitner <richard.leitner@linux.dev> <me@g0hl1n.net> 
Richard Leitner <richard.leitner@linux.dev> <richard.leitner@skidata.com>

Robert Foss <rfoss@kernel.org> <robert.foss@linaro.org>

Rocky Liao <quic_rjliao@quicinc.com> <rjliao@codeaurora.org>

Rodrigo Siqueira <siqueira@igalia.com> <rodrigosiqueiramelo@gmail.com>

Rodrigo Siqueira <siqueira@igalia.com> <Rodrigo.Siqueira@amd.com>

Roman Gushchin <roman.gushchin@linux.dev> <guro@fb.com>

Roman Gushchin <roman.gushchin@linux.dev> <guroan@gmail.com>

Roman Gushchin <roman.gushchin@linux.dev> <klamm@yandex-team.ru>

Documentation/gpu/amdgpu/amdgpu-glossary.rst

+42 −3
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@@ -12,6 +12,9 @@ we have a dedicated glossary for Display Core at 
      The number of CUs that are active on the system.  The number of active

      CUs may be less than SE * SH * CU depending on the board configuration.



    CE

      Constant Engine



    CP

      Command Processor
@@ -68,6 +71,9 @@ we have a dedicated glossary for Display Core at 
    IB

      Indirect Buffer



    IMU

      Integrated Management Unit (Power Management support)



    IP

        Intellectual Property blocks
@@ -80,6 +86,12 @@ we have a dedicated glossary for Display Core at 
    KIQ

      Kernel Interface Queue



    MC

      Memory Controller



    ME

      MicroEngine (Graphics)



    MEC

      MicroEngine Compute
@@ -92,6 +104,9 @@ we have a dedicated glossary for Display Core at 
    MQD

      Memory Queue Descriptor



    PFP

      Pre-Fetch Parser (Graphics)



    PPLib

      PowerPlay Library - PowerPlay is the power management component.
@@ -99,7 +114,10 @@ we have a dedicated glossary for Display Core at 
        Platform Security Processor



    RLC

      RunList Controller

      RunList Controller. This name is a remnant of past ages and doesn't have

      much meaning today. It's a group of general-purpose helper engines for

      the GFX block. It's involved in GFX power management and SR-IOV, among

      other things.



    SDMA

      System DMA
@@ -110,14 +128,35 @@ we have a dedicated glossary for Display Core at 
    SH

      SHader array



    SMU

      System Management Unit

    SMU/SMC

      System Management Unit / System Management Controller



    SRLC

      Save/Restore List Control



    SRLG

      Save/Restore List GPM_MEM



    SRLS

      Save/Restore List SRM_MEM



    SS

      Spread Spectrum



    TA

      Trusted Application



    TOC

      Table of Contents



    UVD

      Unified Video Decoder



    VCE

      Video Compression Engine



    VCN

      Video Codec Next



    VPE

      Video Processing Engine

Documentation/gpu/amdgpu/display/dc-glossary.rst

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@@ -167,9 +167,6 @@ consider asking in the amdgfx and update this page. 
    MALL

      Memory Access at Last Level



    MC

      Memory Controller



    MPC/MPCC

      Multiple pipes and plane combine
@@ -232,6 +229,3 @@ consider asking in the amdgfx and update this page. 


    VRR

      Variable Refresh Rate
 


    UVD

      Unified Video Decoder

MAINTAINERS

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@@ -1046,14 +1046,14 @@ F: drivers/crypto/ccp/hsti.* 
AMD DISPLAY CORE

M:	Harry Wentland <harry.wentland@amd.com>

M:	Leo Li <sunpeng.li@amd.com>

M:	Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>

R:	Rodrigo Siqueira <siqueira@igalia.com>

L:	amd-gfx@lists.freedesktop.org

S:	Supported

T:	git https://gitlab.freedesktop.org/agd5f/linux.git

F:	drivers/gpu/drm/amd/display/









AMD DISPLAY CORE - DML









M:	Chaitanya Dhere <chaitanya.dhere@amd.com>









M:	Austin Zheng <austin.zheng@amd.com>









M:	Jun Lei <jun.lei@amd.com>









S:	Supported









F:	drivers/gpu/drm/amd/display/dc/dml/








@@ -19681,7 +19681,6 @@ F:	drivers/net/wireless/quantenna







RADEON and AMDGPU DRM DRIVERS









M:	Alex Deucher <alexander.deucher@amd.com>









M:	Christian König <christian.koenig@amd.com>









M:	Xinhui Pan <Xinhui.Pan@amd.com>









L:	amd-gfx@lists.freedesktop.org









S:	Supported









B:	https://gitlab.freedesktop.org/drm/amd/-/issues

























drivers/gpu/drm/amd/amdgpu/amdgpu.h



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−0






























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@@ -1192,6 +1192,7 @@ struct amdgpu_device {







	bool                            debug_use_vram_fw_buf;









	bool                            debug_enable_ras_aca;









	bool                            debug_exp_resets;









	bool                            debug_disable_gpu_ring_reset;



















	bool				enforce_isolation[MAX_XCP];









	/* Added this mutex for cleaner shader isolation between GFX and compute processes */