Commit 23d5ec3f authored by JC Kuo's avatar JC Kuo Committed by Thierry Reding
Browse files

phy: tegra: xusb: Move usb3 port init for Tegra210 



The programming sequence in tegra210_usb3_port_enable() is required
for both cold boot and SC7 exit, and must be performed only after
PEX/SATA UPHY is initialized. Therefore, this commit moves the
programming sequence to tegra210_usb3_phy_power_on(). PCIE/SATA phy
.power_on() stub will invoke tegra210_usb3_phy_power_on() if the lane
is assigned for XUSB super-speed.

Signed-off-by: default avatarJC Kuo <jckuo@nvidia.com>
Acked-By: default avatarVinod Koul <vkoul@kernel.org>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 6efb943b

drivers/phy/tegra/xusb-tegra210.c

+175 −141
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.

 * Copyright (c) 2014-2020, NVIDIA CORPORATION.  All rights reserved.

 * Copyright (C) 2015 Google, Inc.

 */
@@ -256,6 +256,32 @@ to_tegra210_xusb_padctl(struct tegra_xusb_padctl *padctl) 
	return container_of(padctl, struct tegra210_xusb_padctl, base);

}



static const struct tegra_xusb_lane_map tegra210_usb3_map[] = {

	{ 0, "pcie", 6 },

	{ 1, "pcie", 5 },

	{ 2, "pcie", 0 },

	{ 2, "pcie", 3 },

	{ 3, "pcie", 4 },

	{ 3, "sata", 0 },

	{ 0, NULL,   0 }

};



static int tegra210_usb3_lane_map(struct tegra_xusb_lane *lane)

{

	const struct tegra_xusb_lane_map *map;



	for (map = tegra210_usb3_map; map->type; map++) {

		if (map->index == lane->index &&

		    strcmp(map->type, lane->pad->soc->name) == 0) {

			dev_dbg(lane->pad->padctl->dev, "lane = %s map to port = usb3-%d\n",

				lane->pad->soc->lanes[lane->index].name, map->port);

			return map->port;

		}

	}



	return -EINVAL;

}



/* must be called under padctl->lock */

static int tegra210_pex_uphy_enable(struct tegra_xusb_padctl *padctl)

{
@@ -470,19 +496,14 @@ static void tegra210_pex_uphy_disable(struct tegra_xusb_padctl *padctl) 
{

	struct tegra_xusb_pcie_pad *pcie = to_pcie_pad(padctl->pcie);



	mutex_lock(&padctl->lock);



	if (WARN_ON(pcie->enable == 0))

		goto unlock;

		return;



	if (--pcie->enable > 0)

		goto unlock;

		return;



	reset_control_assert(pcie->rst);

	clk_disable_unprepare(pcie->pll);



unlock:

	mutex_unlock(&padctl->lock);

}



/* must be called under padctl->lock */
@@ -712,19 +733,14 @@ static void tegra210_sata_uphy_disable(struct tegra_xusb_padctl *padctl) 
{

	struct tegra_xusb_sata_pad *sata = to_sata_pad(padctl->sata);



	mutex_lock(&padctl->lock);



	if (WARN_ON(sata->enable == 0))

		goto unlock;

		return;



	if (--sata->enable > 0)

		goto unlock;

		return;



	reset_control_assert(sata->rst);

	clk_disable_unprepare(sata->pll);



unlock:

	mutex_unlock(&padctl->lock);

}



static int tegra210_xusb_padctl_enable(struct tegra_xusb_padctl *padctl)
@@ -1599,6 +1615,128 @@ static const struct tegra_xusb_lane_soc tegra210_pcie_lanes[] = { 
	TEGRA210_LANE("pcie-6", 0x028, 24, 0x3, pcie),

};



static struct tegra_xusb_usb3_port *

tegra210_lane_to_usb3_port(struct tegra_xusb_lane *lane)

{

	int port;



	if (!lane || !lane->pad || !lane->pad->padctl)

		return NULL;



	port = tegra210_usb3_lane_map(lane);

	if (port < 0)

		return NULL;



	return tegra_xusb_find_usb3_port(lane->pad->padctl, port);

}



static int tegra210_usb3_phy_power_on(struct phy *phy)

{

	struct device *dev = &phy->dev;

	struct tegra_xusb_lane *lane = phy_get_drvdata(phy);

	struct tegra_xusb_padctl *padctl = lane->pad->padctl;

	struct tegra_xusb_usb3_port *usb3 = tegra210_lane_to_usb3_port(lane);

	unsigned int index;

	u32 value;



	if (!usb3) {

		dev_err(dev, "no USB3 port found for lane %u\n", lane->index);

		return -ENODEV;

	}



	index = usb3->base.index;



	value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP);



	if (!usb3->internal)

		value &= ~XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(index);

	else

		value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(index);



	value &= ~XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK(index);

	value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(index, usb3->port);

	padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_MAP);



	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_USB3_PADX_ECTL1(index));

	value &= ~(XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_MASK <<

		   XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_SHIFT);

	value |= XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_VAL <<

		 XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_SHIFT;

	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_USB3_PADX_ECTL1(index));



	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_USB3_PADX_ECTL2(index));

	value &= ~(XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_MASK <<

		   XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_SHIFT);

	value |= XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_VAL <<

		 XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_SHIFT;

	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_USB3_PADX_ECTL2(index));



	padctl_writel(padctl, XUSB_PADCTL_UPHY_USB3_PAD_ECTL3_RX_DFE_VAL,

		      XUSB_PADCTL_UPHY_USB3_PADX_ECTL3(index));



	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_USB3_PADX_ECTL4(index));

	value &= ~(XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_MASK <<

		   XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_SHIFT);

	value |= XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_VAL <<

		 XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_SHIFT;

	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_USB3_PADX_ECTL4(index));



	padctl_writel(padctl, XUSB_PADCTL_UPHY_USB3_PAD_ECTL6_RX_EQ_CTRL_H_VAL,

		      XUSB_PADCTL_UPHY_USB3_PADX_ECTL6(index));



	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);

	value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(index);

	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);



	usleep_range(100, 200);



	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);

	value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(index);

	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);



	usleep_range(100, 200);



	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);

	value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(index);

	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);



	return 0;

}



static int tegra210_usb3_phy_power_off(struct phy *phy)

{

	struct device *dev = &phy->dev;

	struct tegra_xusb_lane *lane = phy_get_drvdata(phy);

	struct tegra_xusb_padctl *padctl = lane->pad->padctl;

	struct tegra_xusb_usb3_port *usb3 = tegra210_lane_to_usb3_port(lane);

	unsigned int index;

	u32 value;



	if (!usb3) {

		dev_err(dev, "no USB3 port found for lane %u\n", lane->index);

		return -ENODEV;

	}



	index = usb3->base.index;



	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);

	value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(index);

	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);



	usleep_range(100, 200);



	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);

	value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(index);

	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);



	usleep_range(250, 350);



	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);

	value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(index);

	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);



	return 0;

}

static struct tegra_xusb_lane *

tegra210_pcie_lane_probe(struct tegra_xusb_pad *pad, struct device_node *np,

			 unsigned int index)
@@ -1668,6 +1806,9 @@ static int tegra210_pcie_phy_power_on(struct phy *phy) 
	value |= XUSB_PADCTL_USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->index);

	padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX);



	if (tegra_xusb_lane_check(lane, "usb3-ss"))

		err = tegra210_usb3_phy_power_on(phy);



unlock:

	mutex_unlock(&padctl->lock);

	return err;
@@ -1677,15 +1818,22 @@ static int tegra210_pcie_phy_power_off(struct phy *phy) 
{

	struct tegra_xusb_lane *lane = phy_get_drvdata(phy);

	struct tegra_xusb_padctl *padctl = lane->pad->padctl;

	int err = 0;

	u32 value;



	mutex_lock(&padctl->lock);



	value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX);

	value &= ~XUSB_PADCTL_USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->index);

	padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX);



	tegra210_pex_uphy_disable(padctl);



	return 0;

	if (tegra_xusb_lane_check(lane, "usb3-ss"))

		err = tegra210_usb3_phy_power_off(phy);



	mutex_unlock(&padctl->lock);

	return err;

}



static const struct phy_ops tegra210_pcie_phy_ops = {
@@ -1839,6 +1987,9 @@ static int tegra210_sata_phy_power_on(struct phy *phy) 
	value |= XUSB_PADCTL_USB3_PAD_MUX_SATA_IDDQ_DISABLE(lane->index);

	padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX);



	if (tegra_xusb_lane_check(lane, "usb3-ss"))

		err = tegra210_usb3_phy_power_on(phy);



unlock:

	mutex_unlock(&padctl->lock);

	return err;
@@ -1848,15 +1999,22 @@ static int tegra210_sata_phy_power_off(struct phy *phy) 
{

	struct tegra_xusb_lane *lane = phy_get_drvdata(phy);

	struct tegra_xusb_padctl *padctl = lane->pad->padctl;

	int err = 0;

	u32 value;



	mutex_lock(&padctl->lock);



	value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX);

	value &= ~XUSB_PADCTL_USB3_PAD_MUX_SATA_IDDQ_DISABLE(lane->index);

	padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX);



	tegra210_sata_uphy_disable(lane->pad->padctl);



	return 0;

	if (tegra_xusb_lane_check(lane, "usb3-ss"))

		err = tegra210_usb3_phy_power_off(phy);



	mutex_unlock(&padctl->lock);

	return err;

}



static const struct phy_ops tegra210_sata_phy_ops = {
@@ -1984,137 +2142,13 @@ static const struct tegra_xusb_port_ops tegra210_hsic_port_ops = { 


static int tegra210_usb3_port_enable(struct tegra_xusb_port *port)

{

	struct tegra_xusb_usb3_port *usb3 = to_usb3_port(port);

	struct tegra_xusb_padctl *padctl = port->padctl;

	struct tegra_xusb_lane *lane = usb3->base.lane;

	unsigned int index = port->index;

	u32 value;

	int err;



	value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP);



	if (!usb3->internal)

		value &= ~XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(index);

	else

		value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(index);



	value &= ~XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK(index);

	value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(index, usb3->port);

	padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_MAP);



	/*

	 * TODO: move this code into the PCIe/SATA PHY ->power_on() callbacks

	 * and conditionalize based on mux function? This seems to work, but

	 * might not be the exact proper sequence.

	 */

	err = regulator_enable(usb3->supply);

	if (err < 0)

		return err;



	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_USB3_PADX_ECTL1(index));

	value &= ~(XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_MASK <<

		   XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_SHIFT);

	value |= XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_VAL <<

		 XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_SHIFT;

	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_USB3_PADX_ECTL1(index));



	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_USB3_PADX_ECTL2(index));

	value &= ~(XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_MASK <<

		   XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_SHIFT);

	value |= XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_VAL <<

		 XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_SHIFT;

	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_USB3_PADX_ECTL2(index));



	padctl_writel(padctl, XUSB_PADCTL_UPHY_USB3_PAD_ECTL3_RX_DFE_VAL,

		      XUSB_PADCTL_UPHY_USB3_PADX_ECTL3(index));



	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_USB3_PADX_ECTL4(index));

	value &= ~(XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_MASK <<

		   XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_SHIFT);

	value |= XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_VAL <<

		 XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_SHIFT;

	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_USB3_PADX_ECTL4(index));



	padctl_writel(padctl, XUSB_PADCTL_UPHY_USB3_PAD_ECTL6_RX_EQ_CTRL_H_VAL,

		      XUSB_PADCTL_UPHY_USB3_PADX_ECTL6(index));



	if (lane->pad == padctl->sata)

		err = tegra210_sata_uphy_enable(padctl, true);

	else

		err = tegra210_pex_uphy_enable(padctl);



	if (err) {

		dev_err(&port->dev, "%s: failed to enable UPHY: %d\n",

			__func__, err);

		return err;

	}



	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);

	value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(index);

	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);



	usleep_range(100, 200);



	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);

	value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(index);

	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);



	usleep_range(100, 200);



	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);

	value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(index);

	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);



	return 0;

}



static void tegra210_usb3_port_disable(struct tegra_xusb_port *port)

{

	struct tegra_xusb_usb3_port *usb3 = to_usb3_port(port);

	struct tegra_xusb_padctl *padctl = port->padctl;

	struct tegra_xusb_lane *lane = port->lane;

	unsigned int index = port->index;

	u32 value;



	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);

	value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(index);

	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);



	usleep_range(100, 200);



	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);

	value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(index);

	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);



	usleep_range(250, 350);



	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);

	value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(index);

	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);



	if (lane->pad == padctl->sata)

		tegra210_sata_uphy_disable(padctl);

	else

		tegra210_pex_uphy_disable(padctl);



	regulator_disable(usb3->supply);



	value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP);

	value &= ~XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK(index);

	value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(index, 0x7);

	padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_MAP);

}



static const struct tegra_xusb_lane_map tegra210_usb3_map[] = {

	{ 0, "pcie", 6 },

	{ 1, "pcie", 5 },

	{ 2, "pcie", 0 },

	{ 2, "pcie", 3 },

	{ 3, "pcie", 4 },

	{ 3, "pcie", 4 },

	{ 0, NULL,   0 }

};



static struct tegra_xusb_lane *

tegra210_usb3_port_map(struct tegra_xusb_port *port)

{

drivers/phy/tegra/xusb.c

+2 −2
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2014-2016, NVIDIA CORPORATION.  All rights reserved.

 * Copyright (c) 2014-2020, NVIDIA CORPORATION.  All rights reserved.

 */



#include <linux/delay.h>
@@ -376,7 +376,7 @@ static int tegra_xusb_setup_pads(struct tegra_xusb_padctl *padctl) 
	return 0;

}



static bool tegra_xusb_lane_check(struct tegra_xusb_lane *lane,

bool tegra_xusb_lane_check(struct tegra_xusb_lane *lane,

				  const char *function)

{

	const char *func = lane->soc->funcs[lane->function];

drivers/phy/tegra/xusb.h

+3 −1
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2014-2015, NVIDIA CORPORATION.  All rights reserved.

 * Copyright (c) 2014-2020, NVIDIA CORPORATION.  All rights reserved.

 * Copyright (c) 2015, Google Inc.

 */
@@ -128,6 +128,8 @@ struct tegra_xusb_lane_ops { 
	void (*remove)(struct tegra_xusb_lane *lane);

};



bool tegra_xusb_lane_check(struct tegra_xusb_lane *lane, const char *function);



/*

 * pads

 */