Commit 23dee18f authored by Ovidiu Bunea's avatar Ovidiu Bunea Committed by Alex Deucher
Browse files

drm/amd/display: Add min clock init for DML21 mode programming 



[WHY & HOW]
0 stream cases do not go through any DML validation which leaves DCN
clocks in unoptimized states.

If requesting DML validation or programming with 0 streams, program
DCN clocks to lowest DPM state.

Reviewed-by: default avatarDillon Varone <dillon.varone@amd.com>
Signed-off-by: default avatarOvidiu Bunea <ovidiu.bunea@amd.com>
Signed-off-by: default avatarAlex Hung <alex.hung@amd.com>
Tested-by: default avatarDan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent aef320b0

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c

+25 −0
Original line number Diff line number Diff line
@@ -931,3 +931,28 @@ void dml21_set_dc_p_state_type( 
	}

}



void dml21_init_min_clocks_for_dc_state(struct dml2_context *in_ctx, struct dc_state *context)

{

	unsigned int lowest_dpm_state_index = 0;

	struct dc_clocks *min_clocks = &context->bw_ctx.bw.dcn.clk;



	min_clocks->dispclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.clk_values_khz[lowest_dpm_state_index];

	min_clocks->dppclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.clk_values_khz[lowest_dpm_state_index];

	min_clocks->dcfclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.dcfclk.clk_values_khz[lowest_dpm_state_index];

	min_clocks->dramclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.uclk.clk_values_khz[lowest_dpm_state_index];

	min_clocks->fclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.fclk.clk_values_khz[lowest_dpm_state_index];

	min_clocks->idle_dramclk_khz = 0;

	min_clocks->idle_fclk_khz = 0;

	min_clocks->dcfclk_deep_sleep_khz = 0;

	min_clocks->fclk_p_state_change_support = true;

	min_clocks->p_state_change_support = true;

	min_clocks->dtbclk_en = false;

	min_clocks->ref_dtbclk_khz = 0;

	min_clocks->socclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.socclk.clk_values_khz[lowest_dpm_state_index];

	min_clocks->subvp_prefetch_dramclk_khz = 0;

	min_clocks->subvp_prefetch_fclk_khz = 0;

	min_clocks->phyclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.phyclk.clk_values_khz[lowest_dpm_state_index];

	min_clocks->stutter_efficiency.base_efficiency = 1;

	min_clocks->stutter_efficiency.low_power_efficiency = 1;

}

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.h

+1 −0
Original line number Diff line number Diff line
@@ -25,4 +25,5 @@ void dml21_map_hw_resources(struct dml2_context *dml_ctx); 
void dml21_get_pipe_mcache_config(struct dc_state *context, struct pipe_ctx *pipe_ctx, struct dml2_per_plane_programming *pln_prog, struct dml2_pipe_configuration_descriptor *mcache_pipe_config);

void dml21_set_dc_p_state_type(struct pipe_ctx *pipe_ctx, struct dml2_per_stream_programming *stream_programming, bool sub_vp_enabled);

unsigned int map_plane_to_dml21_display_cfg(const struct dml2_context *dml_ctx, unsigned int stream_id, const struct dc_plane_state *plane, const struct dc_state *context);

void dml21_init_min_clocks_for_dc_state(struct dml2_context *in_ctx, struct dc_state *context);

#endif

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c

+1 −0
Original line number Diff line number Diff line
@@ -215,6 +215,7 @@ static bool dml21_mode_check_and_programming(const struct dc *in_dc, struct dc_s 
		return true;



	if (context->stream_count == 0) {

		dml21_init_min_clocks_for_dc_state(dml_ctx, context);

		dml21_build_fams2_programming(in_dc, context, dml_ctx);

		return true;

	}