Merge tag 'mfd-next-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd

        clock-names = "msi", "ahb";

        power-domains = <&pd IMX_SC_R_DC_0>;

        syscon@56221000 {

            compatible = "fsl,imx8qxp-mipi-lvds-csr", "syscon", "simple-mfd";

        bus@56221000 {

            compatible = "simple-pm-bus", "syscon";

            reg = <0x56221000 0x1000>;

            clocks = <&mipi_lvds_0_di_mipi_lvds_regs_lpcg IMX_LPCG_CLK_4>;

            clock-names = "ipg";

            #address-cells = <1>;

            #size-cells = <1>;

            ranges;

            pxl2dpi {

                compatible = "fsl,imx8qxp-pxl2dpi";

* NXP LPC1850 CREG clocks

The NXP LPC18xx/43xx CREG (Configuration Registers) block contains

control registers for two low speed clocks. One of the clocks is a

32 kHz oscillator driver with power up/down and clock gating. Next

is a fixed divider that creates a 1 kHz clock from the 32 kHz osc.

These clocks are used by the RTC and the Event Router peripherals.

The 32 kHz can also be routed to other peripherals to enable low

power modes.

This binding uses the common clock binding:

    Documentation/devicetree/bindings/clock/clock-bindings.txt

Required properties:

- compatible:

	Should be "nxp,lpc1850-creg-clk"

- #clock-cells:

	Shall have value <1>.

- clocks:

	Shall contain a phandle to the fixed 32 kHz crystal.

The creg-clk node must be a child of the creg syscon node.

The following clocks are available from the clock node.

Clock ID	Name

   0		 1 kHz clock

   1		32 kHz Oscillator

Example:

soc {

	creg: syscon@40043000 {

		compatible = "nxp,lpc1850-creg", "syscon", "simple-mfd";

		reg = <0x40043000 0x1000>;

		creg_clk: clock-controller {

			compatible = "nxp,lpc1850-creg-clk";

			clocks = <&xtal32>;

			#clock-cells = <1>;

		};

		...

	};

	rtc: rtc@40046000 {

		...

		clocks = <&creg_clk 0>, <&ccu1 CLK_CPU_BUS>;

		clock-names = "rtc", "reg";

		...

	};

};

NXP LPC18xx/43xx DMA MUX (DMA request router)

Required properties:

- compatible:	"nxp,lpc1850-dmamux"

- reg:		Memory map for accessing module

- #dma-cells:	Should be set to <3>.

		* 1st cell contain the master dma request signal

		* 2nd cell contain the mux value (0-3) for the peripheral

		* 3rd cell contain either 1 or 2 depending on the AHB

		  master used.

- dma-requests:	Number of DMA requests for the mux

- dma-masters:	phandle pointing to the DMA controller

The DMA controller node need to have the following poroperties:

- dma-requests:	Number of DMA requests the controller can handle

Example:

dmac: dma@40002000 {

	compatible = "nxp,lpc1850-gpdma", "arm,pl080", "arm,primecell";

	arm,primecell-periphid = <0x00041080>;

	reg = <0x40002000 0x1000>;

	interrupts = <2>;

	clocks = <&ccu1 CLK_CPU_DMA>;

	clock-names = "apb_pclk";

	#dma-cells = <2>;

	dma-channels = <8>;

	dma-requests = <16>;

	lli-bus-interface-ahb1;

	lli-bus-interface-ahb2;

	mem-bus-interface-ahb1;

	mem-bus-interface-ahb2;

	memcpy-burst-size = <256>;

	memcpy-bus-width = <32>;

};

dmamux: dma-mux {

	compatible = "nxp,lpc1850-dmamux";

	#dma-cells = <3>;

	dma-requests = <64>;

	dma-masters = <&dmac>;

};

uart0: serial@40081000 {

	compatible = "nxp,lpc1850-uart", "ns16550a";

	reg = <0x40081000 0x1000>;

	reg-shift = <2>;

	interrupts = <24>;

	clocks = <&ccu2 CLK_APB0_UART0>, <&ccu1 CLK_CPU_UART0>;

	clock-names = "uartclk", "reg";

	dmas = <&dmamux 1 1 2

		&dmamux 2 1 2>;

	dma-names = "tx", "rx";

};

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/mfd/fsl,imx8qxp-csr.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale i.MX8qm/qxp Control and Status Registers Module

maintainers:

  - Liu Ying <victor.liu@nxp.com>

description: |

  As a system controller, the Freescale i.MX8qm/qxp Control and Status

  Registers(CSR) module represents a set of miscellaneous registers of a

  specific subsystem.  It may provide control and/or status report interfaces

  to a mix of standalone hardware devices within that subsystem.  One typical

  use-case is for some other nodes to acquire a reference to the syscon node

  by phandle, and the other typical use-case is that the operating system

  should consider all subnodes of the CSR module as separate child devices.

properties:

  $nodename:

    pattern: "^syscon@[0-9a-f]+$"

  compatible:

    items:

      - enum:

          - fsl,imx8qxp-mipi-lvds-csr

          - fsl,imx8qm-lvds-csr

      - const: syscon

      - const: simple-mfd

  reg:

    maxItems: 1

  clocks:

    maxItems: 1

  clock-names:

    const: ipg

patternProperties:

  "^(ldb|phy|pxl2dpi)$":

    type: object

    description: The possible child devices of the CSR module.

required:

  - compatible

  - reg

  - clocks

  - clock-names

allOf:

  - if:

      properties:

        compatible:

          contains:

            const: fsl,imx8qxp-mipi-lvds-csr

    then:

      required:

        - pxl2dpi

        - ldb

  - if:

      properties:

        compatible:

          contains:

            const: fsl,imx8qm-lvds-csr

    then:

      required:

        - phy

        - ldb

additionalProperties: false

examples:

  - |

    #include <dt-bindings/clock/imx8-lpcg.h>

    #include <dt-bindings/firmware/imx/rsrc.h>

    mipi_lvds_0_csr: syscon@56221000 {

        compatible = "fsl,imx8qxp-mipi-lvds-csr", "syscon", "simple-mfd";

        reg = <0x56221000 0x1000>;

        clocks = <&mipi_lvds_0_di_mipi_lvds_regs_lpcg IMX_LPCG_CLK_4>;

        clock-names = "ipg";

        mipi_lvds_0_pxl2dpi: pxl2dpi {

            compatible = "fsl,imx8qxp-pxl2dpi";

            fsl,sc-resource = <IMX_SC_R_MIPI_0>;

            power-domains = <&pd IMX_SC_R_MIPI_0>;

            ports {

                #address-cells = <1>;

                #size-cells = <0>;

                port@0 {

                    #address-cells = <1>;

                    #size-cells = <0>;

                    reg = <0>;

                    mipi_lvds_0_pxl2dpi_dc0_pixel_link0: endpoint@0 {

                        reg = <0>;

                        remote-endpoint = <&dc0_pixel_link0_mipi_lvds_0_pxl2dpi>;

                    };

                    mipi_lvds_0_pxl2dpi_dc0_pixel_link1: endpoint@1 {

                        reg = <1>;

                        remote-endpoint = <&dc0_pixel_link1_mipi_lvds_0_pxl2dpi>;

                    };

                };

                port@1 {

                    #address-cells = <1>;

                    #size-cells = <0>;

                    reg = <1>;

                    mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0: endpoint@0 {

                        reg = <0>;

                        remote-endpoint = <&mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi>;

                    };

                    mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1: endpoint@1 {

                        reg = <1>;

                        remote-endpoint = <&mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi>;

                    };

                };

            };

        };

        mipi_lvds_0_ldb: ldb {

            #address-cells = <1>;

            #size-cells = <0>;

            compatible = "fsl,imx8qxp-ldb";

            clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>,

                     <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>;

            clock-names = "pixel", "bypass";

            power-domains = <&pd IMX_SC_R_LVDS_0>;

            channel@0 {

                #address-cells = <1>;

                #size-cells = <0>;

                reg = <0>;

                phys = <&mipi_lvds_0_phy>;

                phy-names = "lvds_phy";

                port@0 {

                    reg = <0>;

                    mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi: endpoint {

                        remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0>;

                    };

                };

                port@1 {

                    reg = <1>;

                    /* ... */

                };

            };

            channel@1 {

                #address-cells = <1>;

                #size-cells = <0>;

                reg = <1>;

                phys = <&mipi_lvds_0_phy>;

                phy-names = "lvds_phy";

                port@0 {

                    reg = <0>;

                    mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi: endpoint {

                        remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1>;

                    };

                };

                port@1 {

                    reg = <1>;

                    /* ... */

                };

            };

        };

    };

    mipi_lvds_0_phy: phy@56228300 {

        compatible = "fsl,imx8qxp-mipi-dphy";

        reg = <0x56228300 0x100>;

        clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_PHY>;

        clock-names = "phy_ref";

        #phy-cells = <0>;

        fsl,syscon = <&mipi_lvds_0_csr>;

        power-domains = <&pd IMX_SC_R_MIPI_0>;

    };

* Freescale MXS LRADC device driver

Required properties:

- compatible: Should be "fsl,imx23-lradc" for i.MX23 SoC and "fsl,imx28-lradc"

              for i.MX28 SoC

- reg: Address and length of the register set for the device

- interrupts: Should contain the LRADC interrupts

Optional properties:

- fsl,lradc-touchscreen-wires: Number of wires used to connect the touchscreen

                               to LRADC. Valid value is either 4 or 5. If this

                               property is not present, then the touchscreen is

                               disabled. 5 wires is valid for i.MX28 SoC only.

- fsl,ave-ctrl: number of samples per direction to calculate an average value.

                Allowed value is 1 ... 32, default is 4

- fsl,ave-delay: delay between consecutive samples. Allowed value is

                 2 ... 2048. It is used if 'fsl,ave-ctrl' > 1, counts at

                 2 kHz and its default is 2 (= 1 ms)

- fsl,settling: delay between plate switch to next sample. Allowed value is

                1 ... 2047. It counts at 2 kHz and its default is

                10 (= 5 ms)

Example for i.MX23 SoC:

	lradc@80050000 {

		compatible = "fsl,imx23-lradc";

		reg = <0x80050000 0x2000>;

		interrupts = <36 37 38 39 40 41 42 43 44>;

		fsl,lradc-touchscreen-wires = <4>;

		fsl,ave-ctrl = <4>;

		fsl,ave-delay = <2>;

		fsl,settling = <10>;

	};

Example for i.MX28 SoC:

	lradc@80050000 {

		compatible = "fsl,imx28-lradc";

		reg = <0x80050000 0x2000>;

		interrupts = <10 14 15 16 17 18 19 20 21 22 23 24 25>;

		fsl,lradc-touchscreen-wires = <5>;

		fsl,ave-ctrl = <4>;

		fsl,ave-delay = <2>;

		fsl,settling = <10>;

	};