Commit 24fdd518 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'loongarch-6.8' of... 

Merge tag 'loongarch-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson

Pull LoongArch updates from Huacai Chen:

 - Raise minimum clang version to 18.0.0

 - Enable initial Rust support for LoongArch

 - Add built-in dtb support for LoongArch

 - Use generic interface to support crashkernel=X,[high,low]

 - Some bug fixes and other small changes

 - Update the default config file.

* tag 'loongarch-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson: (22 commits)
  MAINTAINERS: Add BPF JIT for LOONGARCH entry
  LoongArch: Update Loongson-3 default config file
  LoongArch: BPF: Prevent out-of-bounds memory access
  LoongArch: BPF: Support 64-bit pointers to kfuncs
  LoongArch: Fix definition of ftrace_regs_set_instruction_pointer()
  LoongArch: Use generic interface to support crashkernel=X,[high,low]
  LoongArch: Fix and simplify fcsr initialization on execve()
  LoongArch: Let cores_io_master cover the largest NR_CPUS
  LoongArch: Change SHMLBA from SZ_64K to PAGE_SIZE
  LoongArch: Add a missing call to efi_esrt_init()
  LoongArch: Parsing CPU-related information from DTS
  LoongArch: dts: DeviceTree for Loongson-2K2000
  LoongArch: dts: DeviceTree for Loongson-2K1000
  LoongArch: dts: DeviceTree for Loongson-2K0500
  LoongArch: Allow device trees be built into the kernel
  dt-bindings: interrupt-controller: loongson,liointc: Fix dtbs_check warning for interrupt-names
  dt-bindings: interrupt-controller: loongson,liointc: Fix dtbs_check warning for reg-names
  dt-bindings: loongarch: Add Loongson SoC boards compatibles
  dt-bindings: loongarch: Add CPU bindings for LoongArch
  LoongArch: Enable initial Rust support
  ...
parents 9bc44c51 6e441fa3

Documentation/admin-guide/kernel-parameters.txt

+13 −11
Original line number Diff line number Diff line
@@ -888,9 +888,9 @@ 
			memory region [offset, offset + size] for that kernel

			image. If '@offset' is omitted, then a suitable offset

			is selected automatically.

			[KNL, X86-64, ARM64, RISCV] Select a region under 4G first, and

			fall back to reserve region above 4G when '@offset'

			hasn't been specified.

			[KNL, X86-64, ARM64, RISCV, LoongArch] Select a region

			under 4G first, and fall back to reserve region above

			4G when '@offset' hasn't been specified.

			See Documentation/admin-guide/kdump/kdump.rst for further details.



	crashkernel=range1:size1[,range2:size2,...][@offset]
@@ -901,25 +901,27 @@ 
			Documentation/admin-guide/kdump/kdump.rst for an example.



	crashkernel=size[KMG],high

			[KNL, X86-64, ARM64, RISCV] range could be above 4G.

			[KNL, X86-64, ARM64, RISCV, LoongArch] range could be

			above 4G.

			Allow kernel to allocate physical memory region from top,

			so could be above 4G if system have more than 4G ram

			installed. Otherwise memory region will be allocated

			below 4G, if available.

			It will be ignored if crashkernel=X is specified.

	crashkernel=size[KMG],low

			[KNL, X86-64, ARM64, RISCV] range under 4G. When crashkernel=X,high

			is passed, kernel could allocate physical memory region

			above 4G, that cause second kernel crash on system

			that require some amount of low memory, e.g. swiotlb

			requires at least 64M+32K low memory, also enough extra

			low memory is needed to make sure DMA buffers for 32-bit

			devices won't run out. Kernel would try to allocate

			[KNL, X86-64, ARM64, RISCV, LoongArch] range under 4G.

			When crashkernel=X,high is passed, kernel could allocate

			physical memory region above 4G, that cause second kernel

			crash on system that require some amount of low memory,

			e.g. swiotlb requires at least 64M+32K low memory, also

			enough extra low memory is needed to make sure DMA buffers

			for 32-bit devices won't run out. Kernel would try to allocate

			default	size of memory below 4G automatically. The default

			size is	platform dependent.

			  --> x86: max(swiotlb_size_or_default() + 8MiB, 256MiB)

			  --> arm64: 128MiB

			  --> riscv: 128MiB

			  --> loongarch: 128MiB

			This one lets the user specify own low range under 4G

			for second kernel instead.

			0: to disable low allocation.

Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml

+12 −6
Original line number Diff line number Diff line
@@ -11,8 +11,13 @@ maintainers: 


description: |

  This interrupt controller is found in the Loongson-3 family of chips and

  Loongson-2K1000 chip, as the primary package interrupt controller which

  Loongson-2K series chips, as the primary package interrupt controller which

  can route local I/O interrupt to interrupt lines of cores.

  Be aware of the following points.

  1.The Loongson-2K0500 is a single core CPU;

  2.The Loongson-2K0500/2K1000 has 64 device interrupt sources as inputs, so we

    need to define two nodes in dts{i} to describe the "0-31" and "32-61" interrupt

    sources respectively.



allOf:

  - $ref: /schemas/interrupt-controller.yaml#
@@ -33,6 +38,7 @@ properties: 
      - const: main

      - const: isr0

      - const: isr1

    minItems: 2



  interrupt-controller: true
@@ -45,11 +51,9 @@ properties: 
  interrupt-names:

    description: List of names for the parent interrupts.

    items:

      - const: int0

      - const: int1

      - const: int2

      - const: int3

      pattern: int[0-3]

    minItems: 1

    maxItems: 4



  '#interrupt-cells':

    const: 2
@@ -69,6 +73,7 @@ required: 
  - compatible

  - reg

  - interrupts

  - interrupt-names

  - interrupt-controller

  - '#interrupt-cells'

  - loongson,parent_int_map
@@ -86,7 +91,8 @@ if: 
then:

  properties:

    reg:

      minItems: 3

      minItems: 2

      maxItems: 3



  required:

    - reg-names

Documentation/devicetree/bindings/loongarch/cpus.yaml

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+61 −0
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/loongarch/cpus.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: LoongArch CPUs



maintainers:

  - Binbin Zhou <zhoubinbin@loongson.cn>



description:

  This document describes the list of LoongArch CPU cores that support FDT,

  it describe the layout of CPUs in a system through the "cpus" node.



allOf:

  - $ref: /schemas/cpu.yaml#



properties:

  compatible:

    enum:

      - loongson,la264

      - loongson,la364



  reg:

    maxItems: 1



  clocks:

    maxItems: 1



required:

  - compatible

  - reg

  - clocks



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/loongson,ls2k-clk.h>



    cpus {

        #size-cells = <0>;

        #address-cells = <1>;



        cpu@0 {

            compatible = "loongson,la264";

            device_type = "cpu";

            reg = <0>;

            clocks = <&clk LOONGSON2_NODE_CLK>;

        };



        cpu@1 {

            compatible = "loongson,la264";

            device_type = "cpu";

            reg = <1>;

            clocks = <&clk LOONGSON2_NODE_CLK>;

        };

    };



...

Documentation/devicetree/bindings/loongarch/loongson.yaml

0 → 100644
+34 −0
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/loongarch/loongson.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Loongson SoC-based boards



maintainers:

  - Binbin Zhou <zhoubinbin@loongson.cn>



properties:

  $nodename:

    const: '/'

  compatible:

    oneOf:

      - description: Loongson-2K0500 processor based boards

        items:

          - const: loongson,ls2k0500-ref

          - const: loongson,ls2k0500



      - description: Loongson-2K1000 processor based boards

        items:

          - const: loongson,ls2k1000-ref

          - const: loongson,ls2k1000



      - description: Loongson-2K2000 processor based boards

        items:

          - const: loongson,ls2k2000-ref

          - const: loongson,ls2k2000



additionalProperties: true



...

Documentation/rust/arch-support.rst

+7 −6
Original line number Diff line number Diff line
@@ -12,10 +12,11 @@ which uses ``libclang``. 
Below is a general summary of architectures that currently work. Level of

support corresponds to ``S`` values in the ``MAINTAINERS`` file.



============  ================  ==============================================

=============  ================  ==============================================

Architecture   Level of support  Constraints

============  ================  ==============================================

=============  ================  ==============================================

``loongarch``  Maintained        -

``um``         Maintained        ``x86_64`` only.

``x86``        Maintained        ``x86_64`` only.

============  ================  ==============================================

=============  ================  ==============================================