Commit 25294cb8 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2025-06-14' of https://gitlab.freedesktop.org/drm/kernel 

Pull drm fixes from Dave Airlie:
 "Quiet week, only two pull requests came my way, xe has a couple of
  fixes and then a bunch of fixes across the board, vc4 probably fixes
  the biggest problem:

  vc4:
   - Fix infinite EPROBE_DEFER loop in vc4 probing

  amdxdna:
   - Fix amdxdna firmware size

  meson:
   - modesetting fixes

  sitronix:
   - Kconfig fix for st7171-i2c

  dma-buf:
   - Fix -EBUSY WARN_ON_ONCE in dma-buf

  udmabuf:
   - Use dma_sync_sgtable_for_cpu in udmabuf

  xe:
   - Fix regression disallowing 64K SVM migration
   - Use a bounce buffer for WA BB"

* tag 'drm-fixes-2025-06-14' of https://gitlab.freedesktop.org/drm/kernel:
  drm/xe/lrc: Use a temporary buffer for WA BB
  udmabuf: use sgtable-based scatterlist wrappers
  dma-buf: fix compare in WARN_ON_ONCE
  drm/sitronix: st7571-i2c: Select VIDEOMODE_HELPERS
  drm/meson: fix more rounding issues with 59.94Hz modes
  drm/meson: use vclk_freq instead of pixel_freq in debug print
  drm/meson: fix debug log statement when setting the HDMI clocks
  drm/vc4: fix infinite EPROBE_DEFER loop
  drm/xe/svm: Fix regression disallowing 64K SVM migration
  accel/amdxdna: Fix incorrect PSP firmware size
parents 18531f4d 1364af9c

drivers/accel/amdxdna/aie2_psp.c

+2 −2
Original line number Diff line number Diff line
@@ -126,8 +126,8 @@ struct psp_device *aie2m_psp_create(struct drm_device *ddev, struct psp_config * 
	psp->ddev = ddev;

	memcpy(psp->psp_regs, conf->psp_regs, sizeof(psp->psp_regs));



	psp->fw_buf_sz = ALIGN(conf->fw_size, PSP_FW_ALIGN) + PSP_FW_ALIGN;

	psp->fw_buffer = drmm_kmalloc(ddev, psp->fw_buf_sz, GFP_KERNEL);

	psp->fw_buf_sz = ALIGN(conf->fw_size, PSP_FW_ALIGN);

	psp->fw_buffer = drmm_kmalloc(ddev, psp->fw_buf_sz + PSP_FW_ALIGN, GFP_KERNEL);

	if (!psp->fw_buffer) {

		drm_err(ddev, "no memory for fw buffer");

		return NULL;

drivers/dma-buf/dma-buf.c

+1 −1
Original line number Diff line number Diff line
@@ -1118,7 +1118,7 @@ struct sg_table *dma_buf_map_attachment(struct dma_buf_attachment *attach, 
		 * Catch exporters making buffers inaccessible even when

		 * attachments preventing that exist.

		 */

		WARN_ON_ONCE(ret == EBUSY);

		WARN_ON_ONCE(ret == -EBUSY);

		if (ret)

			return ERR_PTR(ret);

	}

drivers/dma-buf/udmabuf.c

+2 −3
Original line number Diff line number Diff line
@@ -264,8 +264,7 @@ static int begin_cpu_udmabuf(struct dma_buf *buf, 
			ubuf->sg = NULL;

		}

	} else {

		dma_sync_sg_for_cpu(dev, ubuf->sg->sgl, ubuf->sg->nents,

				    direction);

		dma_sync_sgtable_for_cpu(dev, ubuf->sg, direction);

	}



	return ret;
@@ -280,7 +279,7 @@ static int end_cpu_udmabuf(struct dma_buf *buf, 
	if (!ubuf->sg)

		return -EINVAL;



	dma_sync_sg_for_device(dev, ubuf->sg->sgl, ubuf->sg->nents, direction);

	dma_sync_sgtable_for_device(dev, ubuf->sg, direction);

	return 0;

}

drivers/gpu/drm/meson/meson_encoder_hdmi.c

+1 −1
Original line number Diff line number Diff line
@@ -109,7 +109,7 @@ static void meson_encoder_hdmi_set_vclk(struct meson_encoder_hdmi *encoder_hdmi, 
		venc_freq /= 2;



	dev_dbg(priv->dev,

		"vclk:%lluHz phy=%lluHz venc=%lluHz hdmi=%lluHz enci=%d\n",

		"phy:%lluHz vclk=%lluHz venc=%lluHz hdmi=%lluHz enci=%d\n",

		phy_freq, vclk_freq, venc_freq, hdmi_freq,

		priv->venc.hdmi_use_enci);

drivers/gpu/drm/meson/meson_vclk.c

+34 −21
Original line number Diff line number Diff line
@@ -110,10 +110,7 @@ 
#define HDMI_PLL_LOCK		BIT(31)

#define HDMI_PLL_LOCK_G12A	(3 << 30)



#define PIXEL_FREQ_1000_1001(_freq)	\

	DIV_ROUND_CLOSEST_ULL((_freq) * 1000ULL, 1001ULL)

#define PHY_FREQ_1000_1001(_freq)	\

	(PIXEL_FREQ_1000_1001(DIV_ROUND_DOWN_ULL(_freq, 10ULL)) * 10)

#define FREQ_1000_1001(_freq)	DIV_ROUND_CLOSEST_ULL((_freq) * 1000ULL, 1001ULL)



/* VID PLL Dividers */

enum {
@@ -772,6 +769,36 @@ static void meson_hdmi_pll_generic_set(struct meson_drm *priv, 
		  pll_freq);

}



static bool meson_vclk_freqs_are_matching_param(unsigned int idx,

						unsigned long long phy_freq,

						unsigned long long vclk_freq)

{

	DRM_DEBUG_DRIVER("i = %d vclk_freq = %lluHz alt = %lluHz\n",

			 idx, params[idx].vclk_freq,

			 FREQ_1000_1001(params[idx].vclk_freq));

	DRM_DEBUG_DRIVER("i = %d phy_freq = %lluHz alt = %lluHz\n",

			 idx, params[idx].phy_freq,

			 FREQ_1000_1001(params[idx].phy_freq));



	/* Match strict frequency */

	if (phy_freq == params[idx].phy_freq &&

	    vclk_freq == params[idx].vclk_freq)

		return true;



	/* Match 1000/1001 variant: vclk deviation has to be less than 1kHz

	 * (drm EDID is defined in 1kHz steps, so everything smaller must be

	 * rounding error) and the PHY freq deviation has to be less than

	 * 10kHz (as the TMDS clock is 10 times the pixel clock, so anything

	 * smaller must be rounding error as well).

	 */

	if (abs(vclk_freq - FREQ_1000_1001(params[idx].vclk_freq)) < 1000 &&

	    abs(phy_freq - FREQ_1000_1001(params[idx].phy_freq)) < 10000)

		return true;



	/* no match */

	return false;

}



enum drm_mode_status

meson_vclk_vic_supported_freq(struct meson_drm *priv,

			      unsigned long long phy_freq,
@@ -790,19 +817,7 @@ meson_vclk_vic_supported_freq(struct meson_drm *priv, 
	}



	for (i = 0 ; params[i].pixel_freq ; ++i) {

		DRM_DEBUG_DRIVER("i = %d pixel_freq = %lluHz alt = %lluHz\n",

				 i, params[i].pixel_freq,

				 PIXEL_FREQ_1000_1001(params[i].pixel_freq));

		DRM_DEBUG_DRIVER("i = %d phy_freq = %lluHz alt = %lluHz\n",

				 i, params[i].phy_freq,

				 PHY_FREQ_1000_1001(params[i].phy_freq));

		/* Match strict frequency */

		if (phy_freq == params[i].phy_freq &&

		    vclk_freq == params[i].vclk_freq)

			return MODE_OK;

		/* Match 1000/1001 variant */

		if (phy_freq == PHY_FREQ_1000_1001(params[i].phy_freq) &&

		    vclk_freq == PIXEL_FREQ_1000_1001(params[i].vclk_freq))

		if (meson_vclk_freqs_are_matching_param(i, phy_freq, vclk_freq))

			return MODE_OK;

	}
@@ -1075,10 +1090,8 @@ void meson_vclk_setup(struct meson_drm *priv, unsigned int target, 
	}



	for (freq = 0 ; params[freq].pixel_freq ; ++freq) {

		if ((phy_freq == params[freq].phy_freq ||

		     phy_freq == PHY_FREQ_1000_1001(params[freq].phy_freq)) &&

		    (vclk_freq == params[freq].vclk_freq ||

		     vclk_freq == PIXEL_FREQ_1000_1001(params[freq].vclk_freq))) {

		if (meson_vclk_freqs_are_matching_param(freq, phy_freq,

							vclk_freq)) {

			if (vclk_freq != params[freq].vclk_freq)

				vic_alternate_clock = true;

			else