Commit 2563391e authored by Chaitanya Dhere's avatar Chaitanya Dhere Committed by Alex Deucher
Browse files

drm/amd/display: DML2.1 resynchronization 



July update for DML2.1 library from hardware team targeting DCN401

Reviewed-by: default avatarAurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: default avatarJerry Zuo <jerry.zuo@amd.com>
Signed-off-by: default avatarChaitanya Dhere <chaitanya.dhere@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 5d2c102d

drivers/gpu/drm/amd/display/dc/dml2/Makefile

+0 −3
Original line number Diff line number Diff line
@@ -87,7 +87,6 @@ CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_factory.o := $(dml2_c 
CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_dcn4.o := $(dml2_ccflags)

CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_factory.o := $(dml2_ccflags)

CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.o := $(dml2_ccflags)

CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4.o := $(dml2_ccflags)

CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.o := $(dml2_ccflags)

CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_factory.o := $(dml2_ccflags)

CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_standalone_libraries/lib_float_math.o := $(dml2_ccflags)
@@ -110,7 +109,6 @@ CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_factory.o := $ 
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_dcn4.o := $(dml2_rcflags)

CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_factory.o := $(dml2_rcflags)

CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.o := $(dml2_rcflags)

CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4.o := $(dml2_rcflags)

CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.o := $(dml2_rcflags)

CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_factory.o := $(dml2_rcflags)

CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_standalone_libraries/lib_float_math.o := $(dml2_rcflags)
@@ -132,7 +130,6 @@ DML21 += src/dml2_dpmm/dml2_dpmm_factory.o 
DML21 += src/dml2_mcg/dml2_mcg_dcn4.o

DML21 += src/dml2_mcg/dml2_mcg_factory.o

DML21 += src/dml2_pmo/dml2_pmo_dcn3.o

DML21 += src/dml2_pmo/dml2_pmo_dcn4.o

DML21 += src/dml2_pmo/dml2_pmo_factory.o

DML21 += src/dml2_pmo/dml2_pmo_dcn4_fams2.o

DML21 += src/dml2_standalone_libraries/lib_float_math.o

drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/bounding_boxes/dcn4_soc_bb.h

+10 −3
Original line number Diff line number Diff line
@@ -344,6 +344,9 @@ static const struct dml2_ip_capabilities dml2_dcn401_max_ip_caps = { 
	.config_return_buffer_segment_size_in_kbytes = 64,

	.meta_fifo_size_in_kentries = 22,

	.compressed_buffer_segment_size_in_kbytes = 64,

	.max_flip_time_us = 80,

	.max_flip_time_lines = 32,

	.hostvm_mode = 0,

	.subvp_drr_scheduling_margin_us = 100,

	.subvp_prefetch_end_to_mall_start_us = 15,

	.subvp_fw_processing_delay = 15,
@@ -351,14 +354,18 @@ static const struct dml2_ip_capabilities dml2_dcn401_max_ip_caps = { 


	.fams2 = {

		.max_allow_delay_us = 100 * 1000,

		.scheduling_delay_us = 50,

		.scheduling_delay_us = 125,

		.vertical_interrupt_ack_delay_us = 18,

		.allow_programming_delay_us = 18,

		.min_allow_width_us = 20,

		.subvp_df_throttle_delay_us = 100,

		.subvp_programming_delay_us = 18,

		.subvp_programming_delay_us = 200,

		.subvp_prefetch_to_mall_delay_us = 18,

		.drr_programming_delay_us = 18,

		.drr_programming_delay_us = 35,



		.lock_timeout_us = 5000,

		.recovery_timeout_us = 5000,

		.flip_programming_delay_us = 300,

	},

};

drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top.h

+0 −1
Original line number Diff line number Diff line
@@ -2,7 +2,6 @@ 
//

// Copyright 2024 Advanced Micro Devices, Inc.





#ifndef __DML_TOP_H__

#define __DML_TOP_H__

drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h

+0 −1
Original line number Diff line number Diff line
@@ -2,7 +2,6 @@ 
//

// Copyright 2024 Advanced Micro Devices, Inc.





#ifndef __dml2_TOP_DCHUB_REGISTERS_H__

#define __dml2_TOP_DCHUB_REGISTERS_H__

drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_display_cfg_types.h

+1 −1
Original line number Diff line number Diff line
@@ -2,7 +2,6 @@ 
//

// Copyright 2024 Advanced Micro Devices, Inc.





#ifndef __DML_TOP_DISPLAY_CFG_TYPES_H__

#define __DML_TOP_DISPLAY_CFG_TYPES_H__
@@ -478,6 +477,7 @@ struct dml2_display_cfg { 
		bool max_outstanding_when_urgent_expected_disable;

		bool enable_subvp_implicit_pmo; //enables PMO to switch pipe uclk strategy to subvp, and generate phantom programming

		unsigned int best_effort_min_active_latency_hiding_us;

		bool all_streams_blanked;

	} overrides;

};