Commit 2568b8b0 authored by Nicolas Frattaroli's avatar Nicolas Frattaroli Committed by Boris Brezillon
Browse files

dt-bindings: gpu: mali-valhall-csf: Add shader-present nvmem cell 



On the MediaTek MT8196 SoC, the bitmask for which shader cores are
present and functional is not the one in the Mali GPU's registers, but
in an external efuse.

Add the nvmem cell properties to describe such a setup, and make them
required on MT8196.

Reviewed-by: default avatarRob Herring (Arm) <robh@kernel.org>
Signed-off-by: default avatarNicolas Frattaroli <nicolas.frattaroli@collabora.com>
Link: https://patch.msgid.link/20251220-mt8196-shader-present-v2-1-45b1ff1dfab0@collabora.com


Signed-off-by: default avatarBoris Brezillon <boris.brezillon@collabora.com>
parent 1f61d735

Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml

+14 −0
Original line number Diff line number Diff line
@@ -51,6 +51,14 @@ properties: 
          - stacks

      - const: stacks



  nvmem-cells:

    items:

      - description: bitmask of functional shader cores



  nvmem-cell-names:

    items:

      - const: shader-present



  mali-supply: true



  operating-points-v2: true
@@ -108,6 +116,8 @@ allOf: 
      properties:

        clocks:

          minItems: 3

        nvmem-cells: false

        nvmem-cell-names: false

        power-domains:

          maxItems: 1

        power-domain-names: false
@@ -133,6 +143,8 @@ allOf: 
            - const: core

            - const: stacks

      required:

        - nvmem-cells

        - nvmem-cell-names

        - power-domains



examples:
@@ -179,6 +191,8 @@ examples: 
                     <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH 0>,

                     <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH 0>;

        interrupt-names = "job", "mmu", "gpu";

        nvmem-cells = <&shader_present>;

        nvmem-cell-names = "shader-present";

        power-domains = <&gpufreq>;

    };