Commit 2575db50 authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915/reg: fix g4x pipe data/link m/n register style 



Adhere to the style described at the top of i915_reg.h.

Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/f55960ce8cdcf654e5de19274c7b67b3d3497550.1725974820.git.jani.nikula@intel.com


Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
parent d3944104

drivers/gpu/drm/i915/i915_reg.h

+4 −7
Original line number Diff line number Diff line
@@ -1554,16 +1554,16 @@ 
 */

#define _PIPEA_DATA_M_G4X	0x70050

#define _PIPEB_DATA_M_G4X	0x71050



#define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)

/* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */

#define  TU_SIZE_MASK		REG_GENMASK(30, 25)

#define  TU_SIZE(x)		REG_FIELD_PREP(TU_SIZE_MASK, (x) - 1) /* default size 64 */



#define  DATA_LINK_M_N_MASK	REG_GENMASK(23, 0)

#define  DATA_LINK_N_MAX	(0x800000)



#define _PIPEA_DATA_N_G4X	0x70054

#define _PIPEB_DATA_N_G4X	0x71054

#define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)



/*

 * Computing Link M and N values for the Display Port link
@@ -1575,15 +1575,12 @@ 
 * The Link value is transmitted in the Main Stream

 * Attributes and VB-ID.

 */



#define _PIPEA_LINK_M_G4X	0x70060

#define _PIPEB_LINK_M_G4X	0x71060

#define PIPE_LINK_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X)



#define _PIPEA_LINK_N_G4X	0x70064

#define _PIPEB_LINK_N_G4X	0x71064



#define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)

#define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)

#define PIPE_LINK_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X)

#define PIPE_LINK_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X)



/* Pipe A */