Commit 25a915fa authored by Miquel Raynal's avatar Miquel Raynal
Browse files

mtd: spinand: winbond: Clarify when to enable the HS bit 



Above 104MHz when in fast dual or quad I/O reads, the delay between
address and data cycles is too short. It is possible to reach higher
frequencies, up to 166MHz, by adding a few more dummy cycles through the
setting of the HS bit. Improve the condition for enabling this bit, and
also make sure we set it at soon as we go over 104MHz.

Fixes: f1a91175 ("mtd: spinand: winbond: Enable high-speed modes on w25n0xjw")
Signed-off-by: default avatarMiquel Raynal <miquel.raynal@bootlin.com>
parent 54dcd6aa

drivers/mtd/nand/spi/winbond.c

+8 −5
Original line number Diff line number Diff line
@@ -337,16 +337,19 @@ static int w25n0xjw_hs_cfg(struct spinand_device *spinand, 
	if (iface != SSDR)

		return -EOPNOTSUPP;



	/*

	 * SDR dual and quad I/O operations over 104MHz require the HS bit to

	 * enable a few more dummy cycles.

	 */

	op = spinand->op_templates->read_cache;

	if (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr)

		hs = false;

	else if (op->cmd.buswidth == 1 && op->addr.buswidth == 1 &&

		 op->dummy.buswidth == 1 && op->data.buswidth == 1)

	else if (op->cmd.buswidth != 1 || op->addr.buswidth == 1)

		hs = false;

	else if (!op->max_freq)

		hs = true;

	else

	else if (op->max_freq && op->max_freq <= 104 * HZ_PER_MHZ)

		hs = false;

	else

		hs = true;



	ret = spinand_read_reg_op(spinand, W25N0XJW_SR4, &sr4);

	if (ret)