Commit 2619c62b authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'x86-irq-2026-02-09' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86 irq updates from Thomas Gleixner:
 "Trivial cleanups for the posted MSI interrupt handling"

* tag 'x86-irq-2026-02-09' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/irq_remapping: Sanitize posted_msi_supported()
  x86/irq: Cleanup posted MSI code
parents f1c538ca d441e38a

arch/x86/include/asm/irq_remapping.h

+3 −2
Original line number Diff line number Diff line
@@ -67,9 +67,10 @@ static inline struct irq_domain *arch_get_ir_parent_domain(void) 


extern bool enable_posted_msi;



static inline bool posted_msi_supported(void)

static inline bool posted_msi_enabled(void)

{

	return enable_posted_msi && irq_remapping_cap(IRQ_POSTING_CAP);

	return IS_ENABLED(CONFIG_X86_POSTED_MSI) &&

		enable_posted_msi && irq_remapping_cap(IRQ_POSTING_CAP);

}



#else  /* CONFIG_IRQ_REMAP */

arch/x86/kernel/irq.c

+13 −18
Original line number Diff line number Diff line
@@ -420,11 +420,9 @@ static DEFINE_PER_CPU_CACHE_HOT(bool, posted_msi_handler_active); 


void intel_posted_msi_init(void)

{

	u32 destination;

	u32 apic_id;

	u32 destination, apic_id;



	this_cpu_write(posted_msi_pi_desc.nv, POSTED_MSI_NOTIFICATION_VECTOR);



	/*

	 * APIC destination ID is stored in bit 8:15 while in XAPIC mode.

	 * VT-d spec. CH 9.11
@@ -468,8 +466,8 @@ static __always_inline bool handle_pending_pir(unsigned long *pir, struct pt_reg 
}



/*

 * Performance data shows that 3 is good enough to harvest 90+% of the benefit

 * on high IRQ rate workload.

 * Performance data shows that 3 is good enough to harvest 90+% of the

 * benefit on high interrupt rate workloads.

 */

#define MAX_POSTED_MSI_COALESCING_LOOP 3
@@ -479,11 +477,8 @@ static __always_inline bool handle_pending_pir(unsigned long *pir, struct pt_reg 
 */

DEFINE_IDTENTRY_SYSVEC(sysvec_posted_msi_notification)

{

	struct pi_desc *pid = this_cpu_ptr(&posted_msi_pi_desc);

	struct pt_regs *old_regs = set_irq_regs(regs);

	struct pi_desc *pid;

	int i = 0;



	pid = this_cpu_ptr(&posted_msi_pi_desc);



	/* Mark the handler active for intel_ack_posted_msi_irq() */

	__this_cpu_write(posted_msi_handler_active, true);
@@ -491,25 +486,25 @@ DEFINE_IDTENTRY_SYSVEC(sysvec_posted_msi_notification) 
	irq_enter();



	/*

	 * Max coalescing count includes the extra round of handle_pending_pir

	 * after clearing the outstanding notification bit. Hence, at most

	 * MAX_POSTED_MSI_COALESCING_LOOP - 1 loops are executed here.

	 * Loop only MAX_POSTED_MSI_COALESCING_LOOP - 1 times here to take

	 * the final handle_pending_pir() invocation after clearing the

	 * outstanding notification bit into account.

	 */

	while (++i < MAX_POSTED_MSI_COALESCING_LOOP) {

	for (int i = 1; i < MAX_POSTED_MSI_COALESCING_LOOP; i++) {

		if (!handle_pending_pir(pid->pir, regs))

			break;

	}



	/*

	 * Clear outstanding notification bit to allow new IRQ notifications,

	 * do this last to maximize the window of interrupt coalescing.

	 * Clear the outstanding notification bit to rearm the notification

	 * mechanism.

	 */

	pi_clear_on(pid);



	/*

	 * There could be a race of PI notification and the clearing of ON bit,

	 * process PIR bits one last time such that handling the new interrupts

	 * are not delayed until the next IRQ.

	 * Clearing the ON bit can race with a notification. Process the

	 * PIR bits one last time so that handling the new interrupts is

	 * not delayed until the next notification happens.

	 */

	handle_pending_pir(pid->pir, regs);

drivers/iommu/intel/irq_remapping.c

+2 −2
Original line number Diff line number Diff line
@@ -1368,7 +1368,7 @@ static void intel_irq_remapping_prepare_irte(struct intel_ir_data *data, 
		break;

	case X86_IRQ_ALLOC_TYPE_PCI_MSI:

	case X86_IRQ_ALLOC_TYPE_PCI_MSIX:

		if (posted_msi_supported()) {

		if (posted_msi_enabled()) {

			prepare_irte_posted(irte);

			data->irq_2_iommu.posted_msi = 1;

		}
@@ -1460,7 +1460,7 @@ static int intel_irq_remapping_alloc(struct irq_domain *domain, 


		irq_data->hwirq = (index << 16) + i;

		irq_data->chip_data = ird;

		if (posted_msi_supported() &&

		if (posted_msi_enabled() &&

		    ((info->type == X86_IRQ_ALLOC_TYPE_PCI_MSI) ||

		     (info->type == X86_IRQ_ALLOC_TYPE_PCI_MSIX)))

			irq_data->chip = &intel_ir_chip_post_msi;