Commit 263e5594 authored by Sandipan Das's avatar Sandipan Das Committed by Ingo Molnar
Browse files

x86/cpu/amd: Fix workaround for erratum 1054 



Erratum 1054 affects AMD Zen processors that are a part of Family 17h
Models 00-2Fh and the workaround is to not set HWCR[IRPerfEn]. However,
when X86_FEATURE_ZEN1 was introduced, the condition to detect unaffected
processors was incorrectly changed in a way that the IRPerfEn bit gets
set only for unaffected Zen 1 processors.

Ensure that HWCR[IRPerfEn] is set for all unaffected processors. This
includes a subset of Zen 1 (Family 17h Models 30h and above) and all
later processors. Also clear X86_FEATURE_IRPERF on affected processors
so that the IRPerfCount register is not used by other entities like the
MSR PMU driver.

Fixes: 232afb55 ("x86/CPU/AMD: Add X86_FEATURE_ZEN1")
Signed-off-by: default avatarSandipan Das <sandipan.das@amd.com>
Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
Acked-by: default avatarBorislav Petkov <bp@alien8.de>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/caa057a9d6f8ad579e2f1abaa71efbd5bd4eaf6d.1744956467.git.sandipan.das@amd.com
parent d466304c

arch/x86/kernel/cpu/amd.c

+12 −7
Original line number Diff line number Diff line
@@ -869,6 +869,16 @@ static void init_amd_zen1(struct cpuinfo_x86 *c) 


	pr_notice_once("AMD Zen1 DIV0 bug detected. Disable SMT for full protection.\n");

	setup_force_cpu_bug(X86_BUG_DIV0);



	/*

	 * Turn off the Instructions Retired free counter on machines that are

	 * susceptible to erratum #1054 "Instructions Retired Performance

	 * Counter May Be Inaccurate".

	 */

	if (c->x86_model < 0x30) {

		msr_clear_bit(MSR_K7_HWCR, MSR_K7_HWCR_IRPERF_EN_BIT);

		clear_cpu_cap(c, X86_FEATURE_IRPERF);

	}

}



static bool cpu_has_zenbleed_microcode(void)
@@ -1052,13 +1062,8 @@ static void init_amd(struct cpuinfo_x86 *c) 
	if (!cpu_feature_enabled(X86_FEATURE_XENPV))

		set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS);



	/*

	 * Turn on the Instructions Retired free counter on machines not

	 * susceptible to erratum #1054 "Instructions Retired Performance

	 * Counter May Be Inaccurate".

	 */

	if (cpu_has(c, X86_FEATURE_IRPERF) &&

	    (boot_cpu_has(X86_FEATURE_ZEN1) && c->x86_model > 0x2f))

	/* Enable the Instructions Retired free counter */

	if (cpu_has(c, X86_FEATURE_IRPERF))

		msr_set_bit(MSR_K7_HWCR, MSR_K7_HWCR_IRPERF_EN_BIT);



	check_null_seg_clears_base(c);