Commit 267643b3 authored by Krishna chaitanya chundru's avatar Krishna chaitanya chundru Committed by Bjorn Andersson
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arm64: dts: qcom: qcs6490-rb3gen2: Add PCIe nodes 



Enable PCIe1 controller and its corresponding PHY nodes on
qcs6490-rb3g2 platform.

SMMU v2 has limited SID's to assign dynamic SID's with the existing
logic. For now, use static iommu-map table assigning unique SID's for
each port as dynamic approach needs boarder community discussions.

PCIe switch connected to this board has 3 downstream ports and
to the one of the downstream an embedded ethernet is connected.
Assign unique SID for each downstream port and to embedded ethernet,
and also reserve a SID for the endpoints which are going to be
connected to the other two downstream ports.

As this PCIe switch is present in this platform only update iommu-map
in this platform only as other board variants might have different
PCIe topology and might need different mapping.

Signed-off-by: default avatarKrishna chaitanya chundru <quic_krichai@quicinc.com>
Link: https://lore.kernel.org/r/20241024-enable_pcie-v2-1-e5a6f5da74e4@quicinc.com


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent 06d6fe98

arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts

+41 −0
Original line number Diff line number Diff line
@@ -708,6 +708,32 @@ &mdss_edp_phy { 
	status = "okay";

};



&pcie1 {

	perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;



	pinctrl-0 = <&pcie1_reset_n>, <&pcie1_wake_n>;

	pinctrl-names = "default";



	iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,

		    <0x100 &apps_smmu 0x1c81 0x1>,

		    <0x208 &apps_smmu 0x1c84 0x1>,

		    <0x210 &apps_smmu 0x1c85 0x1>,

		    <0x218 &apps_smmu 0x1c86 0x1>,

		    <0x300 &apps_smmu 0x1c87 0x1>,

		    <0x400 &apps_smmu 0x1c88 0x1>,

		    <0x500 &apps_smmu 0x1c89 0x1>,

		    <0x501 &apps_smmu 0x1c90 0x1>;



	status = "okay";

};



&pcie1_phy {

	vdda-phy-supply = <&vreg_l10c_0p88>;

	vdda-pll-supply = <&vreg_l6b_1p2>;



	status = "okay";

};



&pm7325_gpios {

	kypd_vol_up_n: kypd-vol-up-n-state {

		pins = "gpio6";
@@ -898,6 +924,21 @@ lt9611_irq_pin: lt9611-irq-state { 
		bias-disable;

	};



	pcie1_reset_n: pcie1-reset-n-state {

		pins = "gpio2";

		function = "gpio";

		drive-strength = <16>;

		output-low;

		bias-disable;

	};



	pcie1_wake_n: pcie1-wake-n-state {

		pins = "gpio3";

		function = "gpio";

		drive-strength = <2>;

		bias-pull-up;

	};



	sd_cd: sd-cd-state {

		pins = "gpio91";

		function = "gpio";