Commit 27057882 authored by Dave Airlie's avatar Dave Airlie Committed by Jani Nikula
Browse files

drm/i915: split watermark vfuncs from display vtable. 



These are the watermark api between display and pm.

Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/7130356324ef3de59b4e913f025d7dce822157ee.1632869550.git.jani.nikula@intel.com
parent 46d8e4a1

drivers/gpu/drm/i915/display/intel_display.c

+17 −17
Original line number Diff line number Diff line
@@ -161,16 +161,16 @@ static void intel_modeset_setup_hw_state(struct drm_device *dev, 
 */

static void intel_update_watermarks(struct drm_i915_private *dev_priv)

{

	if (dev_priv->display.update_wm)

		dev_priv->display.update_wm(dev_priv);

	if (dev_priv->wm_disp.update_wm)

		dev_priv->wm_disp.update_wm(dev_priv);

}



static int intel_compute_pipe_wm(struct intel_atomic_state *state,

				 struct intel_crtc *crtc)

{

	struct drm_i915_private *dev_priv = to_i915(state->base.dev);

	if (dev_priv->display.compute_pipe_wm)

		return dev_priv->display.compute_pipe_wm(state, crtc);

	if (dev_priv->wm_disp.compute_pipe_wm)

		return dev_priv->wm_disp.compute_pipe_wm(state, crtc);

	return 0;

}
@@ -178,20 +178,20 @@ static int intel_compute_intermediate_wm(struct intel_atomic_state *state, 
					 struct intel_crtc *crtc)

{

	struct drm_i915_private *dev_priv = to_i915(state->base.dev);

	if (!dev_priv->display.compute_intermediate_wm)

	if (!dev_priv->wm_disp.compute_intermediate_wm)

		return 0;

	if (drm_WARN_ON(&dev_priv->drm,

			!dev_priv->display.compute_pipe_wm))

			!dev_priv->wm_disp.compute_pipe_wm))

		return 0;

	return dev_priv->display.compute_intermediate_wm(state, crtc);

	return dev_priv->wm_disp.compute_intermediate_wm(state, crtc);

}



static bool intel_initial_watermarks(struct intel_atomic_state *state,

				     struct intel_crtc *crtc)

{

	struct drm_i915_private *dev_priv = to_i915(state->base.dev);

	if (dev_priv->display.initial_watermarks) {

		dev_priv->display.initial_watermarks(state, crtc);

	if (dev_priv->wm_disp.initial_watermarks) {

		dev_priv->wm_disp.initial_watermarks(state, crtc);

		return true;

	}

	return false;
@@ -201,23 +201,23 @@ static void intel_atomic_update_watermarks(struct intel_atomic_state *state, 
					   struct intel_crtc *crtc)

{

	struct drm_i915_private *dev_priv = to_i915(state->base.dev);

	if (dev_priv->display.atomic_update_watermarks)

		dev_priv->display.atomic_update_watermarks(state, crtc);

	if (dev_priv->wm_disp.atomic_update_watermarks)

		dev_priv->wm_disp.atomic_update_watermarks(state, crtc);

}



static void intel_optimize_watermarks(struct intel_atomic_state *state,

				      struct intel_crtc *crtc)

{

	struct drm_i915_private *dev_priv = to_i915(state->base.dev);

	if (dev_priv->display.optimize_watermarks)

		dev_priv->display.optimize_watermarks(state, crtc);

	if (dev_priv->wm_disp.optimize_watermarks)

		dev_priv->wm_disp.optimize_watermarks(state, crtc);

}



static int intel_compute_global_watermarks(struct intel_atomic_state *state)

{

	struct drm_i915_private *dev_priv = to_i915(state->base.dev);

	if (dev_priv->display.compute_global_watermarks)

		return dev_priv->display.compute_global_watermarks(state);

	if (dev_priv->wm_disp.compute_global_watermarks)

		return dev_priv->wm_disp.compute_global_watermarks(state);

	return 0;

}
@@ -3743,7 +3743,7 @@ static void i9xx_crtc_disable(struct intel_atomic_state *state, 
	if (DISPLAY_VER(dev_priv) != 2)

		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);



	if (!dev_priv->display.initial_watermarks)

	if (!dev_priv->wm_disp.initial_watermarks)

		intel_update_watermarks(dev_priv);



	/* clock the pipe down to 640x480@60 to potentially save power */
@@ -11404,7 +11404,7 @@ static void sanitize_watermarks(struct drm_i915_private *dev_priv) 
	int i;



	/* Only supported on platforms that use atomic watermark design */

	if (!dev_priv->display.optimize_watermarks)

	if (!dev_priv->wm_disp.optimize_watermarks)

		return;



	state = drm_atomic_state_alloc(&dev_priv->drm);

drivers/gpu/drm/i915/i915_drv.h

+16 −8
Original line number Diff line number Diff line
@@ -328,13 +328,10 @@ struct drm_i915_clock_gating_funcs { 
	void (*init_clock_gating)(struct drm_i915_private *dev_priv);

};



struct drm_i915_display_funcs {

	void (*get_cdclk)(struct drm_i915_private *dev_priv,

			  struct intel_cdclk_config *cdclk_config);

	void (*set_cdclk)(struct drm_i915_private *dev_priv,

			  const struct intel_cdclk_config *cdclk_config,

			  enum pipe pipe);

	int (*bw_calc_min_cdclk)(struct intel_atomic_state *state);

/* functions used for watermark calcs for display. */

struct drm_i915_wm_disp_funcs {

	/* update_wm is for legacy wm management */

	void (*update_wm)(struct drm_i915_private *dev_priv);

	int (*compute_pipe_wm)(struct intel_atomic_state *state,

			       struct intel_crtc *crtc);

	int (*compute_intermediate_wm)(struct intel_atomic_state *state,
@@ -346,7 +343,15 @@ struct drm_i915_display_funcs { 
	void (*optimize_watermarks)(struct intel_atomic_state *state,

				    struct intel_crtc *crtc);

	int (*compute_global_watermarks)(struct intel_atomic_state *state);

	void (*update_wm)(struct drm_i915_private *dev_priv);

};



struct drm_i915_display_funcs {

	void (*get_cdclk)(struct drm_i915_private *dev_priv,

			  struct intel_cdclk_config *cdclk_config);

	void (*set_cdclk)(struct drm_i915_private *dev_priv,

			  const struct intel_cdclk_config *cdclk_config,

			  enum pipe pipe);

	int (*bw_calc_min_cdclk)(struct intel_atomic_state *state);

	int (*modeset_calc_cdclk)(struct intel_cdclk_state *state);

	u8 (*calc_voltage_level)(int cdclk);

	/* Returns the active state of the crtc, and if the crtc is active,
@@ -961,6 +966,9 @@ struct drm_i915_private { 
	/* pm private clock gating functions */

	struct drm_i915_clock_gating_funcs clock_gating_funcs;



	/* pm display functions */

	struct drm_i915_wm_disp_funcs wm_disp;



	/* Display functions */

	struct drm_i915_display_funcs display;

drivers/gpu/drm/i915/intel_pm.c

+20 −20
Original line number Diff line number Diff line
@@ -7960,7 +7960,7 @@ void intel_init_pm(struct drm_i915_private *dev_priv) 
	/* For FIFO watermark updates */

	if (DISPLAY_VER(dev_priv) >= 9) {

		skl_setup_wm_latency(dev_priv);

		dev_priv->display.compute_global_watermarks = skl_compute_wm;

		dev_priv->wm_disp.compute_global_watermarks = skl_compute_wm;

	} else if (HAS_PCH_SPLIT(dev_priv)) {

		ilk_setup_wm_latency(dev_priv);
@@ -7968,12 +7968,12 @@ void intel_init_pm(struct drm_i915_private *dev_priv) 
		     dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||

		    (DISPLAY_VER(dev_priv) != 5 && dev_priv->wm.pri_latency[0] &&

		     dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {

			dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;

			dev_priv->display.compute_intermediate_wm =

			dev_priv->wm_disp.compute_pipe_wm = ilk_compute_pipe_wm;

			dev_priv->wm_disp.compute_intermediate_wm =

				ilk_compute_intermediate_wm;

			dev_priv->display.initial_watermarks =

			dev_priv->wm_disp.initial_watermarks =

				ilk_initial_watermarks;

			dev_priv->display.optimize_watermarks =

			dev_priv->wm_disp.optimize_watermarks =

				ilk_optimize_watermarks;

		} else {

			drm_dbg_kms(&dev_priv->drm,
@@ -7982,17 +7982,17 @@ void intel_init_pm(struct drm_i915_private *dev_priv) 
		}

	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {

		vlv_setup_wm_latency(dev_priv);

		dev_priv->display.compute_pipe_wm = vlv_compute_pipe_wm;

		dev_priv->display.compute_intermediate_wm = vlv_compute_intermediate_wm;

		dev_priv->display.initial_watermarks = vlv_initial_watermarks;

		dev_priv->display.optimize_watermarks = vlv_optimize_watermarks;

		dev_priv->display.atomic_update_watermarks = vlv_atomic_update_fifo;

		dev_priv->wm_disp.compute_pipe_wm = vlv_compute_pipe_wm;

		dev_priv->wm_disp.compute_intermediate_wm = vlv_compute_intermediate_wm;

		dev_priv->wm_disp.initial_watermarks = vlv_initial_watermarks;

		dev_priv->wm_disp.optimize_watermarks = vlv_optimize_watermarks;

		dev_priv->wm_disp.atomic_update_watermarks = vlv_atomic_update_fifo;

	} else if (IS_G4X(dev_priv)) {

		g4x_setup_wm_latency(dev_priv);

		dev_priv->display.compute_pipe_wm = g4x_compute_pipe_wm;

		dev_priv->display.compute_intermediate_wm = g4x_compute_intermediate_wm;

		dev_priv->display.initial_watermarks = g4x_initial_watermarks;

		dev_priv->display.optimize_watermarks = g4x_optimize_watermarks;

		dev_priv->wm_disp.compute_pipe_wm = g4x_compute_pipe_wm;

		dev_priv->wm_disp.compute_intermediate_wm = g4x_compute_intermediate_wm;

		dev_priv->wm_disp.initial_watermarks = g4x_initial_watermarks;

		dev_priv->wm_disp.optimize_watermarks = g4x_optimize_watermarks;

	} else if (IS_PINEVIEW(dev_priv)) {

		if (!intel_get_cxsr_latency(!IS_MOBILE(dev_priv),

					    dev_priv->is_ddr3,
@@ -8006,18 +8006,18 @@ void intel_init_pm(struct drm_i915_private *dev_priv) 
				 dev_priv->fsb_freq, dev_priv->mem_freq);

			/* Disable CxSR and never update its watermark again */

			intel_set_memory_cxsr(dev_priv, false);

			dev_priv->display.update_wm = NULL;

			dev_priv->wm_disp.update_wm = NULL;

		} else

			dev_priv->display.update_wm = pnv_update_wm;

			dev_priv->wm_disp.update_wm = pnv_update_wm;

	} else if (DISPLAY_VER(dev_priv) == 4) {

		dev_priv->display.update_wm = i965_update_wm;

		dev_priv->wm_disp.update_wm = i965_update_wm;

	} else if (DISPLAY_VER(dev_priv) == 3) {

		dev_priv->display.update_wm = i9xx_update_wm;

		dev_priv->wm_disp.update_wm = i9xx_update_wm;

	} else if (DISPLAY_VER(dev_priv) == 2) {

		if (INTEL_NUM_PIPES(dev_priv) == 1)

			dev_priv->display.update_wm = i845_update_wm;

			dev_priv->wm_disp.update_wm = i845_update_wm;

		else

			dev_priv->display.update_wm = i9xx_update_wm;

			dev_priv->wm_disp.update_wm = i9xx_update_wm;

	} else {

		drm_err(&dev_priv->drm,

			"unexpected fall-through in %s\n", __func__);