Commit 270aaae0 authored by Rob Herring (Arm)'s avatar Rob Herring (Arm)
Browse files

dt-bindings: interrupt-controller: Convert marvell,ap806-sei to DT schema

Convert the Marvell SEI interrupt controller binding to schema format.
It's a straight-forward conversion of the typical interrupt controller.

Link: https://lore.kernel.org/r/20250505144749.1290862-1-robh@kernel.org


Reviewed-by: default avatarMiquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: default avatarRob Herring (Arm) <robh@kernel.org>
parent e11b723f
Loading
Loading
Loading
Loading
+58 −0
Original line number Diff line number Diff line
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/marvell,ap806-sei.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Marvell SEI (System Error Interrupt) Controller

maintainers:
  - Miquel Raynal <miquel.raynal@bootlin.com>

description: >
  Marvell SEI (System Error Interrupt) controller is an interrupt aggregator. It
  receives interrupts from several sources and aggregates them to a single
  interrupt line (an SPI) on the parent interrupt controller.

  This interrupt controller can handle up to 64 SEIs, a set comes from the AP
  and is wired while a second set comes from the CPs by the mean of MSIs.

properties:
  compatible:
    const: marvell,ap806-sei

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  '#interrupt-cells':
    const: 1

  interrupt-controller: true

  msi-controller: true

required:
  - compatible
  - reg
  - interrupts
  - '#interrupt-cells'
  - interrupt-controller
  - msi-controller

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    interrupt-controller@3f0200 {
        compatible = "marvell,ap806-sei";
        reg = <0x3f0200 0x40>;
        interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
        #interrupt-cells = <1>;
        interrupt-controller;
        msi-controller;
    };
+0 −36
Original line number Diff line number Diff line
Marvell SEI (System Error Interrupt) Controller
-----------------------------------------------

Marvell SEI (System Error Interrupt) controller is an interrupt
aggregator. It receives interrupts from several sources and aggregates
them to a single interrupt line (an SPI) on the parent interrupt
controller.

This interrupt controller can handle up to 64 SEIs, a set comes from the
AP and is wired while a second set comes from the CPs by the mean of
MSIs.

Required properties:

- compatible: should be one of:
              * "marvell,ap806-sei"
- reg: SEI registers location and length.
- interrupts: identifies the parent IRQ that will be triggered.
- #interrupt-cells: number of cells to define an SEI wired interrupt
                    coming from the AP, should be 1. The cell is the IRQ
                    number.
- interrupt-controller: identifies the node as an interrupt controller
                        for AP interrupts.
- msi-controller: identifies the node as an MSI controller for the CPs
                  interrupts.

Example:

        sei: interrupt-controller@3f0200 {
                compatible = "marvell,ap806-sei";
                reg = <0x3f0200 0x40>;
                interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
                #interrupt-cells = <1>;
                interrupt-controller;
                msi-controller;
        };