Commit 27aec396 authored by Simona Vetter's avatar Simona Vetter
Browse files

Merge tag 'drm-xe-next-2024-07-02' of https://gitlab.freedesktop.org/drm/xe/kernel into drm-next 



Driver Changes:
- Fix in migration code (Auld)
- Simplification in HWMon related code (Karthik)
- Fix in forcewake logic (Nirmoy)
- Fix engine utilization information (umesh)
- Clean up on MOCS related code (Roper)
- Fix on multicast register (Roper)
- Fix TLB invalidation timeout (Nirmoy)
- More SRIOV preparation (Michal)
- Fix out-of-bounds array access (Lucas)
- Fixes around some mutex utilization (Ashutosh, Vinay)
- Expand LNL workaround to BMG (Vinay)

Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/ZoROvquFrTFhk3Pb@intel.com
parents fb625bf6 aaa08078

drivers/gpu/drm/xe/tests/xe_mocs.c

+4 −4
Original line number Diff line number Diff line
@@ -31,9 +31,9 @@ static int live_mocs_init(struct live_mocs *arg, struct xe_gt *gt) 


	kunit_info(test, "gt %d", gt->info.id);

	kunit_info(test, "gt type %d", gt->info.type);

	kunit_info(test, "table size %d", arg->table.size);

	kunit_info(test, "table size %d", arg->table.table_size);

	kunit_info(test, "table uc_index %d", arg->table.uc_index);

	kunit_info(test, "table n_entries %d", arg->table.n_entries);

	kunit_info(test, "table num_mocs_regs %d", arg->table.num_mocs_regs);



	return flags;

}
@@ -50,7 +50,7 @@ static void read_l3cc_table(struct xe_gt *gt, 
	ret = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);

	KUNIT_ASSERT_EQ_MSG(test, ret, 0, "Forcewake Failed.\n");



	for (i = 0; i < info->n_entries; i++) {

	for (i = 0; i < info->num_mocs_regs; i++) {

		if (!(i & 1)) {

			if (regs_are_mcr(gt))

				reg_val = xe_gt_mcr_unicast_read_any(gt, XEHP_LNCFCMOCS(i >> 1));
@@ -90,7 +90,7 @@ static void read_mocs_table(struct xe_gt *gt, 
	ret = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);

	KUNIT_ASSERT_EQ_MSG(test, ret, 0, "Forcewake Failed.\n");



	for (i = 0; i < info->n_entries; i++) {

	for (i = 0; i < info->num_mocs_regs; i++) {

		if (regs_are_mcr(gt))

			reg_val = xe_gt_mcr_unicast_read_any(gt, XEHP_GLOBAL_MOCS(i));

		else

drivers/gpu/drm/xe/xe_drm_client.c

+9 −2
Original line number Diff line number Diff line
@@ -260,13 +260,20 @@ static void show_run_ticks(struct drm_printer *p, struct drm_file *file) 


	/* Get the total GPU cycles */

	for_each_gt(gt, xe, gt_id) {

		enum xe_force_wake_domains fw;



		hwe = xe_gt_any_hw_engine(gt);

		if (!hwe)

			continue;



		xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);

		fw = xe_hw_engine_to_fw_domain(hwe);

		if (xe_force_wake_get(gt_to_fw(gt), fw)) {

			hwe = NULL;

			break;

		}



		gpu_timestamp = xe_hw_engine_read_timestamp(hwe);

		xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);

		XE_WARN_ON(xe_force_wake_put(gt_to_fw(gt), fw));

		break;

	}

drivers/gpu/drm/xe/xe_ggtt.c

+8 −3
Original line number Diff line number Diff line
@@ -74,6 +74,9 @@ static unsigned int probe_gsm_size(struct pci_dev *pdev) 


static void ggtt_update_access_counter(struct xe_ggtt *ggtt)

{

	struct xe_gt *gt = XE_WA(ggtt->tile->primary_gt, 22019338487) ? ggtt->tile->primary_gt :

			   ggtt->tile->media_gt;

	u32 max_gtt_writes = XE_WA(ggtt->tile->primary_gt, 22019338487) ? 1100 : 63;

	/*

	 * Wa_22019338487: GMD_ID is a RO register, a dummy write forces gunit

	 * to wait for completion of prior GTT writes before letting this through.
@@ -81,8 +84,8 @@ static void ggtt_update_access_counter(struct xe_ggtt *ggtt) 
	 */

	lockdep_assert_held(&ggtt->lock);



	if ((++ggtt->access_count % 63) == 0) {

		xe_mmio_write32(ggtt->tile->media_gt, GMD_ID, 0x0);

	if ((++ggtt->access_count % max_gtt_writes) == 0) {

		xe_mmio_write32(gt, GMD_ID, 0x0);

		ggtt->access_count = 0;

	}

}
@@ -218,7 +221,9 @@ int xe_ggtt_init_early(struct xe_ggtt *ggtt) 
		ggtt->size = GUC_GGTT_TOP;



	if (GRAPHICS_VERx100(xe) >= 1270)

		ggtt->pt_ops = ggtt->tile->media_gt && XE_WA(ggtt->tile->media_gt, 22019338487) ?

		ggtt->pt_ops = (ggtt->tile->media_gt &&

			       XE_WA(ggtt->tile->media_gt, 22019338487)) ||

			       XE_WA(ggtt->tile->primary_gt, 22019338487) ?

			       &xelpg_pt_wa_ops : &xelpg_pt_ops;

	else

		ggtt->pt_ops = &xelp_pt_ops;

drivers/gpu/drm/xe/xe_gt.c

+4 −2
Original line number Diff line number Diff line
@@ -683,6 +683,9 @@ static int do_gt_restart(struct xe_gt *gt) 
	/* Restore GT freq to expected values */

	xe_gt_sanitize_freq(gt);



	if (IS_SRIOV_PF(gt_to_xe(gt)))

		xe_gt_sriov_pf_restart(gt);



	return 0;

}
@@ -818,8 +821,7 @@ int xe_gt_sanitize_freq(struct xe_gt *gt) 
	int ret = 0;



	if ((!xe_uc_fw_is_available(&gt->uc.gsc.fw) ||

	    xe_uc_fw_is_loaded(&gt->uc.gsc.fw)) &&

	    XE_WA(gt, 22019338487))

	     xe_uc_fw_is_loaded(&gt->uc.gsc.fw)) && XE_WA(gt, 22019338487))

		ret = xe_guc_pc_restore_stashed_freq(&gt->uc.guc.pc);



	return ret;

drivers/gpu/drm/xe/xe_gt_mcr.c

+3 −3
Original line number Diff line number Diff line
@@ -342,7 +342,7 @@ static void init_steering_oaddrm(struct xe_gt *gt) 
	else

		gt->steering[OADDRM].group_target = 1;



	gt->steering[DSS].instance_target = 0;		/* unused */

	gt->steering[OADDRM].instance_target = 0;	/* unused */

}



static void init_steering_sqidi_psmi(struct xe_gt *gt)
@@ -357,8 +357,8 @@ static void init_steering_sqidi_psmi(struct xe_gt *gt) 


static void init_steering_inst0(struct xe_gt *gt)

{

	gt->steering[DSS].group_target = 0;		/* unused */

	gt->steering[DSS].instance_target = 0;		/* unused */

	gt->steering[INSTANCE0].group_target = 0;	/* unused */

	gt->steering[INSTANCE0].instance_target = 0;	/* unused */

}



static const struct {