Commit 27beb3ca authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'pci-v6.7-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci 

Pull pci updates from Bjorn Helgaas:
 "Enumeration:

   - Use acpi_evaluate_dsm_typed() instead of open-coding _DSM
     evaluation to learn device characteristics (Andy Shevchenko)

   - Tidy multi-function header checks using new PCI_HEADER_TYPE_MASK
     definition (Ilpo Järvinen)

   - Simplify config access error checking in various drivers (Ilpo
     Järvinen)

   - Use pcie_capability_clear_word() (not
     pcie_capability_clear_and_set_word()) when only clearing (Ilpo
     Järvinen)

   - Add pci_get_base_class() to simplify finding devices using base
     class only (ignoring subclass and programming interface) (Sui
     Jingfeng)

   - Add pci_is_vga(), which includes ancient PCI_CLASS_NOT_DEFINED_VGA
     devices from before the Class Code was added to PCI (Sui Jingfeng)

   - Use pci_is_vga() for vgaarb, sysfs "boot_vga", virtio, qxl to
     include ancient VGA devices (Sui Jingfeng)

  Resource management:

   - Make pci_assign_unassigned_resources() non-init because sparc uses
     it after init (Randy Dunlap)

  Driver binding:

   - Retain .remove() and .probe() callbacks (previously __init) because
     sysfs may cause them to be called later (Uwe Kleine-König)

   - Prevent xHCI driver from claiming AMD VanGogh USB3 DRD device, so
     it can be claimed by dwc3 instead (Vicki Pfau)

  PCI device hotplug:

   - Add Ampere Altra Attention Indicator extension driver for acpiphp
     (D Scott Phillips)

  Power management:

   - Quirk VideoPropulsion Torrent QN16e with longer delay after reset
     (Lukas Wunner)

   - Prevent users from overriding drivers that say we shouldn't use
     D3cold (Lukas Wunner)

   - Avoid PME from D3hot/D3cold for AMD Rembrandt and Phoenix USB4
     because wakeup interrupts from those states don't work if amd-pmc
     has put the platform in a hardware sleep state (Mario Limonciello)

  IOMMU:

   - Disable ATS for Intel IPU E2000 devices with invalidation message
     endianness erratum (Bartosz Pawlowski)

  Error handling:

   - Factor out interrupt enable/disable into helpers (Kai-Heng Feng)

  Peer-to-peer DMA:

   - Fix flexible-array usage in struct pci_p2pdma_pagemap in case we
     ever use pagemaps with multiple entries (Gustavo A. R. Silva)

  ASPM:

   - Revert a change that broke when drivers disabled L1 and users later
     enabled an L1.x substate via sysfs, and fix a similar issue when
     users disabled L1 via sysfs (Heiner Kallweit)

  Endpoint framework:

   - Fix double free in __pci_epc_create() (Dan Carpenter)

   - Use IS_ERR_OR_NULL() to simplify endpoint core (Ruan Jinjie)

  Cadence PCIe controller driver:

   - Drop unused "is_rc" member (Li Chen)

  Freescale Layerscape PCIe controller driver:

   - Enable 64-bit addressing in endpoint mode (Guanhua Gao)

  Intel VMD host bridge driver:

   - Fix multi-function header check (Ilpo Järvinen)

  Microsoft Hyper-V host bridge driver:

   - Annotate struct hv_dr_state with __counted_by (Kees Cook)

  NVIDIA Tegra194 PCIe controller driver:

   - Drop setting of LNKCAP_MLW (max link width) since dw_pcie_setup()
     already does this via dw_pcie_link_set_max_link_width() (Yoshihiro
     Shimoda)

  Qualcomm PCIe controller driver:

   - Use PCIE_SPEED2MBS_ENC() to simplify encoding of link speed
     (Manivannan Sadhasivam)

   - Add a .write_dbi2() callback so DBI2 register writes, e.g., for
     setting the BAR size, work correctly (Manivannan Sadhasivam)

   - Enable ASPM for platforms that use 1.9.0 ops, because the PCI core
     doesn't enable ASPM states that haven't been enabled by the
     firmware (Manivannan Sadhasivam)

  Renesas R-Car Gen4 PCIe controller driver:

   - Add DesignWare core support (set max link width, EDMA_UNROLL flag,
     .pre_init(), .deinit(), etc) for use by R-Car Gen4 driver
     (Yoshihiro Shimoda)

   - Add driver and DT schema for DesignWare-based Renesas R-Car Gen4
     controller in both host and endpoint mode (Yoshihiro Shimoda)

  Xilinx NWL PCIe controller driver:

   - Update ECAM size to support 256 buses (Thippeswamy Havalige)

   - Stop setting bridge primary/secondary/subordinate bus numbers,
     since PCI core does this (Thippeswamy Havalige)

  Xilinx XDMA controller driver:

   - Add driver and DT schema for Zynq UltraScale+ MPSoCs devices with
     Xilinx XDMA Soft IP (Thippeswamy Havalige)

  Miscellaneous:

   - Use FIELD_GET()/FIELD_PREP() to simplify and reduce use of _SHIFT
     macros (Ilpo Järvinen, Bjorn Helgaas)

   - Remove logic_outb(), _outw(), outl() duplicate declarations (John
     Sanpe)

   - Replace unnecessary UTF-8 in Kconfig help text because menuconfig
     doesn't render it correctly (Liu Song)"

* tag 'pci-v6.7-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci: (102 commits)
  PCI: qcom-ep: Add dedicated callback for writing to DBI2 registers
  PCI: Simplify pcie_capability_clear_and_set_word() to ..._clear_word()
  PCI: endpoint: Fix double free in __pci_epc_create()
  PCI: xilinx-xdma: Add Xilinx XDMA Root Port driver
  dt-bindings: PCI: xilinx-xdma: Add schemas for Xilinx XDMA PCIe Root Port Bridge
  PCI: xilinx-cpm: Move IRQ definitions to a common header
  PCI: xilinx-nwl: Modify ECAM size to enable support for 256 buses
  PCI: xilinx-nwl: Rename the NWL_ECAM_VALUE_DEFAULT macro
  dt-bindings: PCI: xilinx-nwl: Modify ECAM size in the DT example
  PCI: xilinx-nwl: Remove redundant code that sets Type 1 header fields
  PCI: hotplug: Add Ampere Altra Attention Indicator extension driver
  PCI/AER: Factor out interrupt toggling into helpers
  PCI: acpiphp: Allow built-in drivers for Attention Indicators
  PCI/portdrv: Use FIELD_GET()
  PCI/VC: Use FIELD_GET()
  PCI/PTM: Use FIELD_GET()
  PCI/PME: Use FIELD_GET()
  PCI/ATS: Use FIELD_GET()
  PCI/ATS: Show PASID Capability register width in bitmasks
  PCI/ASPM: Fix L1 substate handling in aspm_attr_store_common()
  ...
parents 4652b8e4 50b3ef14

Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

# Copyright (C) 2022-2023 Renesas Electronics Corp.

%YAML 1.2

---

$id: http://devicetree.org/schemas/pci/rcar-gen4-pci-ep.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Renesas R-Car Gen4 PCIe Endpoint



maintainers:

  - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>



allOf:

  - $ref: snps,dw-pcie-ep.yaml#



properties:

  compatible:

    items:

      - const: renesas,r8a779f0-pcie-ep   # R-Car S4-8

      - const: renesas,rcar-gen4-pcie-ep  # R-Car Gen4



  reg:

    maxItems: 7



  reg-names:

    items:

      - const: dbi

      - const: dbi2

      - const: atu

      - const: dma

      - const: app

      - const: phy

      - const: addr_space



  interrupts:

    maxItems: 3



  interrupt-names:

    items:

      - const: dma

      - const: sft_ce

      - const: app



  clocks:

    maxItems: 2



  clock-names:

    items:

      - const: core

      - const: ref



  power-domains:

    maxItems: 1



  resets:

    maxItems: 1



  reset-names:

    items:

      - const: pwr



  max-link-speed:

    maximum: 4



  num-lanes:

    maximum: 4



  max-functions:

    maximum: 2



required:

  - compatible

  - reg

  - reg-names

  - interrupts

  - interrupt-names

  - clocks

  - clock-names

  - power-domains

  - resets

  - reset-names



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/r8a779f0-cpg-mssr.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/power/r8a779f0-sysc.h>



    soc {

        #address-cells = <2>;

        #size-cells = <2>;



        pcie0_ep: pcie-ep@e65d0000 {

            compatible = "renesas,r8a779f0-pcie-ep", "renesas,rcar-gen4-pcie-ep";

            reg = <0 0xe65d0000 0 0x2000>, <0 0xe65d2000 0 0x1000>,

                  <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>,

                  <0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>,

                  <0 0xfe000000 0 0x400000>;

            reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "addr_space";

            interrupts = <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;

            interrupt-names = "dma", "sft_ce", "app";

            clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>;

            clock-names = "core", "ref";

            power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;

            resets = <&cpg 624>;

            reset-names = "pwr";

            max-link-speed = <4>;

            num-lanes = <2>;

            max-functions = /bits/ 8 <2>;

        };

    };

Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

# Copyright (C) 2022-2023 Renesas Electronics Corp.

%YAML 1.2

---

$id: http://devicetree.org/schemas/pci/rcar-gen4-pci-host.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Renesas R-Car Gen4 PCIe Host



maintainers:

  - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>



allOf:

  - $ref: snps,dw-pcie.yaml#



properties:

  compatible:

    items:

      - const: renesas,r8a779f0-pcie   # R-Car S4-8

      - const: renesas,rcar-gen4-pcie  # R-Car Gen4



  reg:

    maxItems: 7



  reg-names:

    items:

      - const: dbi

      - const: dbi2

      - const: atu

      - const: dma

      - const: app

      - const: phy

      - const: config



  interrupts:

    maxItems: 4



  interrupt-names:

    items:

      - const: msi

      - const: dma

      - const: sft_ce

      - const: app



  clocks:

    maxItems: 2



  clock-names:

    items:

      - const: core

      - const: ref



  power-domains:

    maxItems: 1



  resets:

    maxItems: 1



  reset-names:

    items:

      - const: pwr



  max-link-speed:

    maximum: 4



  num-lanes:

    maximum: 4



required:

  - compatible

  - reg

  - reg-names

  - interrupts

  - interrupt-names

  - clocks

  - clock-names

  - power-domains

  - resets

  - reset-names



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/r8a779f0-cpg-mssr.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/power/r8a779f0-sysc.h>



    soc {

        #address-cells = <2>;

        #size-cells = <2>;



        pcie: pcie@e65d0000 {

            compatible = "renesas,r8a779f0-pcie", "renesas,rcar-gen4-pcie";

            reg = <0 0xe65d0000 0 0x1000>, <0 0xe65d2000 0 0x0800>,

                  <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>,

                  <0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>,

                  <0 0xfe000000 0 0x400000>;

            reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "config";

            interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,

                         <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;

            interrupt-names = "msi", "dma", "sft_ce", "app";

            clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>;

            clock-names = "core", "ref";

            power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;

            resets = <&cpg 624>;

            reset-names = "pwr";

            max-link-speed = <4>;

            num-lanes = <2>;

            #address-cells = <3>;

            #size-cells = <2>;

            bus-range = <0x00 0xff>;

            device_type = "pci";

            ranges = <0x01000000 0 0x00000000 0 0xfe000000 0 0x00400000>,

                     <0x02000000 0 0x30000000 0 0x30000000 0 0x10000000>;

            dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;

            #interrupt-cells = <1>;

            interrupt-map-mask = <0 0 0 7>;

            interrupt-map = <0 0 0 1 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,

                            <0 0 0 2 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,

                            <0 0 0 3 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,

                            <0 0 0 4 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>;

            snps,enable-cdm-check;

        };

    };

Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml

+2 −2
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@@ -33,11 +33,11 @@ properties: 
      specific for each activated function, while the rest of the sub-spaces

      are common for all of them (if there are more than one).

    minItems: 2

    maxItems: 6

    maxItems: 7



  reg-names:

    minItems: 2

    maxItems: 6

    maxItems: 7



  interrupts:

    description:

Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml

+2 −2
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@@ -33,11 +33,11 @@ properties: 
      normal controller functioning. iATU memory IO region is also required

      if the space is unrolled (IP-core version >= 4.80a).

    minItems: 2

    maxItems: 5

    maxItems: 7



  reg-names:

    minItems: 2

    maxItems: 5

    maxItems: 7

    items:

      oneOf:

        - description:

Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml

+2 −2
Original line number Diff line number Diff line
@@ -42,11 +42,11 @@ properties: 
      are required for the normal controller work. iATU memory IO region is

      also required if the space is unrolled (IP-core version >= 4.80a).

    minItems: 2

    maxItems: 5

    maxItems: 7



  reg-names:

    minItems: 2

    maxItems: 5

    maxItems: 7

    items:

      oneOf:

        - description: