Commit 297d9111 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'soc-drivers-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc 

Pull SoC driver updates from Arnd Bergmann:
 "Updates are across the usual driver subsystems with SoC specific
  drivers:

   - added soc specicific drivers for sophgo cv1800 and sg2044, qualcomm
     sm8750, and amlogic c3 and s4 chips.

   - cache controller updates for sifive chips, plus binding changes for
     other cache descriptions.

   - memory controller drivers for mediatek mt6893, stm32 and cleanups
     for a few more drivers

   - reset controller drivers for T-Head TH1502, Sophgo sg2044 and
     Renesas RZ/V2H(P)

   - SCMI firmware updates to better deal with buggy firmware, plus
     better support for Qualcomm X1E and NXP i.MX specific interfaces

   - a new platform driver for the crypto firmware on Cznic Turris
     Omnia/MOX

   - cleanups for the TEE firmware subsystem and amdtee driver

   - minor updates and fixes for freescale/nxp, qualcomm, google,
     aspeed, wondermedia, ti, nxp, renesas, hisilicon, mediatek,
     broadcom and samsung SoCs"

* tag 'soc-drivers-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (133 commits)
  soc: aspeed: Add NULL check in aspeed_lpc_enable_snoop()
  soc: aspeed: lpc: Fix impossible judgment condition
  ARM: aspeed: Don't select SRAM
  docs: firmware: qcom_scm: Fix kernel-doc warning
  soc: fsl: qe: Consolidate chained IRQ handler install/remove
  firmware: qcom: scm: Allow QSEECOM for HP EliteBook Ultra G1q
  dt-bindings: mfd: qcom,tcsr: Add compatible for ipq5018
  dt-bindings: cache: add QiLai compatible to ax45mp
  memory: stm32_omm: Fix error handling in stm32_omm_disable_child()
  dt-bindings: cache: Convert marvell,tauros2-cache to DT schema
  dt-bindings: cache: Convert marvell,{feroceon,kirkwood}-cache to DT schema
  soc: samsung: exynos-pmu: enable CPU hotplug support for gs101
  MAINTAINERS: Add google,gs101-pmu-intr-gen.yaml binding file
  dt-bindings: soc: samsung: exynos-pmu: gs101: add google,pmu-intr-gen phandle
  dt-bindings: soc: google: Add gs101-pmu-intr-gen binding documentation
  bus: fsl-mc: Use strscpy() instead of strscpy_pad()
  soc: fsl: qbman: Remove const from portal->cgrs allocation type
  bus: fsl_mc: Fix driver_managed_dma check
  bus: fsl-mc: increase MC_CMD_COMPLETION_TIMEOUT_MS value
  bus: fsl-mc: drop useless cleanup
  ...
parents 9d49da43 5963edd9

Documentation/ABI/testing/debugfs-scmi-raw

+91 −0
Original line number Diff line number Diff line
@@ -31,6 +31,42 @@ Description: SCMI Raw asynchronous message injection/snooping facility; write 
		(receiving an EOF at each message boundary).

Users:		Debugging, any userspace test suite



What:		/sys/kernel/debug/scmi/<n>/raw/message_poll

Date:		June 2025

KernelVersion:	6.16

Contact:	cristian.marussi@arm.com

Description:	SCMI Raw message injection/snooping facility using polling mode;

		write a complete SCMI command message (header included) in

		little-endian binary format to have it sent to the configured

		backend SCMI server for instance <n>, using polling mode on

		the reception path. (if transport is polling capable)

		Any subsequently received response can be read from this same

		entry if it arrived within the configured timeout.

		Each write to the entry causes one command request to be built

		and sent while the replies are read back one message at time

		(receiving an EOF at each message boundary).

Users:		Debugging, any userspace test suite



What:		/sys/kernel/debug/scmi/<n>/raw/message_poll_async

Date:		June 2025

KernelVersion:	6.16

Contact:	cristian.marussi@arm.com

Description:	SCMI Raw asynchronous message injection/snooping facility using

		polling-mode; write a complete SCMI asynchronous command message

		(header included) in little-endian binary format to have it sent

		to the configured backend SCMI server for instance <n>, using

		polling-mode on the reception path of the immediate part of the

		asynchronous command. (if transport is polling capable)

		Any subsequently received response can be read from this same

		entry if it arrived within the configured timeout.

		Any additional delayed response received afterwards can be read

		from this same entry too if it arrived within the configured

		timeout.

		Each write to the entry causes one command request to be built

		and sent while the replies are read back one message at time

		(receiving an EOF at each message boundary).

Users:		Debugging, any userspace test suite



What:		/sys/kernel/debug/scmi/<n>/raw/errors

Date:		March 2023

KernelVersion:	6.3
@@ -115,3 +151,58 @@ Description: SCMI Raw asynchronous message injection/snooping facility; write 
		exist only if the transport is configured to have more than

		one default channel.

Users:		Debugging, any userspace test suite





What:		/sys/kernel/debug/scmi/<n>/raw/channels/<m>/message_poll

Date:		June 2025

KernelVersion:	6.16

Contact:	cristian.marussi@arm.com

Description:	SCMI Raw message injection/snooping facility using polling mode;

		write a complete SCMI command message (header included) in

		little-endian binary format to have it sent to the configured

		backend SCMI server for instance <n> through the <m> transport

		channel, using polling mode on the reception path.

		(if transport is polling capable)

		Any subsequently received response can be read from this same

		entry if it arrived on channel <m> within the configured

		timeout.

		Each write to the entry causes one command request to be built

		and sent while the replies are read back one message at time

		(receiving an EOF at each message boundary).

		Channel identifier <m> matches the SCMI protocol number which

		has been associated with this transport channel in the DT

		description, with base protocol number 0x10 being the default

		channel for this instance.

		Note that these per-channel entries rooted at <..>/channels

		exist only if the transport is configured to have more than

		one default channel.

Users:		Debugging, any userspace test suite



What:		/sys/kernel/debug/scmi/<n>/raw/channels/<m>/message_poll_async

Date:		June 2025

KernelVersion:	6.16

Contact:	cristian.marussi@arm.com

Description:	SCMI Raw asynchronous message injection/snooping facility using

		polling-mode; write a complete SCMI asynchronous command message

		(header included) in little-endian binary format to have it sent

		to the configured backend SCMI server for instance <n> through

		the <m> transport channel, using polling mode on the reception

		path of the immediate part of the asynchronous command.

		(if transport is polling capable)

		Any subsequently received response can be read from this same

		entry if it arrived on channel <m> within the configured

		timeout.

		Any additional delayed response received afterwards can be read

		from this same entry too if it arrived within the configured

		timeout.

		Each write to the entry causes one command request to be built

		and sent while the replies are read back one message at time

		(receiving an EOF at each message boundary).

		Channel identifier <m> matches the SCMI protocol number which

		has been associated with this transport channel in the DT

		description, with base protocol number 0x10 being the default

		channel for this instance.

		Note that these per-channel entries rooted at <..>/channels

		exist only if the transport is configured to have more than

		one default channel.

Users:		Debugging, any userspace test suite

Documentation/ABI/testing/debugfs-turris-mox-rwtm

deleted100644 → 0
+0 −14
Original line number Diff line number Diff line 
What:		/sys/kernel/debug/turris-mox-rwtm/do_sign

Date:		Jun 2020

KernelVersion:	5.8

Contact:	Marek Behún <kabel@kernel.org>

Description:



		======= ===========================================================

		(Write) Message to sign with the ECDSA private key stored in

		        device's OTP. The message must be exactly 64 bytes

		        (since this is intended for SHA-512 hashes).

		(Read)  The resulting signature, 136 bytes. This contains the

			R and S values of the ECDSA signature, both in

			big-endian format.

		======= ===========================================================

Documentation/ABI/testing/sysfs-firmware-turris-mox-rwtm

+0 −9
Original line number Diff line number Diff line
@@ -12,15 +12,6 @@ Contact: Marek Behún <kabel@kernel.org> 
Description:	(Read) MAC addresses burned into eFuses of this Turris Mox board.

		Format: %pM



What:		/sys/firmware/turris-mox-rwtm/pubkey

Date:		August 2019

KernelVersion:	5.4

Contact:	Marek Behún <kabel@kernel.org>

Description:	(Read) ECDSA public key (in pubkey hex compressed form) computed

		as pair to the ECDSA private key burned into eFuses of this

		Turris Mox Board.

		Format: string



What:		/sys/firmware/turris-mox-rwtm/ram_size

Date:		August 2019

KernelVersion:	5.4

Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml

+19 −1
Original line number Diff line number Diff line
@@ -28,6 +28,9 @@ select: 
properties:

  compatible:

    items:

      - enum:

          - andestech,qilai-ax45mp-cache

          - renesas,r9a07g043f-ax45mp-cache

      - const: andestech,ax45mp-cache

      - const: cache
@@ -65,12 +68,27 @@ required: 
  - cache-size

  - cache-unified



allOf:

  - if:

      properties:

        compatible:

          contains:

            const: andestech,qilai-ax45mp-cache



    then:

      properties:

        cache-sets:

          const: 2048

        cache-size:

          const: 2097152



examples:

  - |

    #include <dt-bindings/interrupt-controller/irq.h>



    cache-controller@13400000 {

        compatible = "andestech,ax45mp-cache", "cache";

        compatible = "renesas,r9a07g043f-ax45mp-cache", "andestech,ax45mp-cache",

                     "cache";

        reg = <0x13400000 0x100000>;

        interrupts = <508 IRQ_TYPE_LEVEL_HIGH>;

        cache-line-size = <64>;

Documentation/devicetree/bindings/cache/marvell,feroceon-cache.txt

deleted100644 → 0
+0 −16
Original line number Diff line number Diff line 
* Marvell Feroceon Cache



Required properties:

- compatible : Should be either "marvell,feroceon-cache" or

  	       "marvell,kirkwood-cache".



Optional properties:

- reg        : Address of the L2 cache control register. Mandatory for

  	       "marvell,kirkwood-cache", not used by "marvell,feroceon-cache"





Example:

		l2: l2-cache@20128 {

			compatible = "marvell,kirkwood-cache";

			reg = <0x20128 0x4>;

		};