Commit 2999e786 authored by André Draszik's avatar André Draszik Committed by Krzysztof Kozlowski
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clk: samsung: gs101: add support for cmu_peric1 



CMU_PERIC1 is the clock management unit used for the peric1 block which
is used for additional USI, I3C and PWM interfaces/busses. Add support
for muxes, dividers and gates of cmu_peric1, except for
CLK_GOUT_PERIC1_IP which isn't well described in the datasheet and
which downstream also ignores (similar to cmu_peric0).

Two clocks have been marked as CLK_IS_CRITICAL for the following
reason:
    * disabling them makes it impossible to access any peric1
      registers, (including those two registers).
    * disabling gout_peric1_lhm_axi_p_peric1_i_clk sometimes has the
      additional effect of making the whole system unresponsive.

One clock marked as CLK_IGNORE_UNUSED needs to be kept on until we have
updated the respective driver for the following reason:
    * gout_peric1_gpio_peric1_pclk is required by the pinctrl
      configuration. With this clock disabled, reconfiguring the pins
      (for USI/I2C, USI/UART) will hang during register access.
      Since pinctrl-samsung doesn't support a clock at the moment, we
      just keep the kernel from disabling it at boot, until we have an
      update for pinctrl-samsung, at which point we'll drop the flag.

Signed-off-by: default avatarAndré Draszik <andre.draszik@linaro.org>
Reviewed-by: default avatarSam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: default avatarPeter Griffin <peter.griffin@linaro.org>
Reviewed-by: default avatarTudor Ambarus <tudor.ambarus@linaro.org>
Link: https://lore.kernel.org/r/20240201161258.1013664-4-andre.draszik@linaro.org


Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
parent 3ab1d817

drivers/clk/samsung/clk-gs101.c

+346 −0
Original line number Diff line number Diff line
@@ -21,6 +21,7 @@ 
#define CLKS_NR_APM	(CLK_APM_PLL_DIV16_APM + 1)

#define CLKS_NR_MISC	(CLK_GOUT_MISC_XIU_D_MISC_ACLK + 1)

#define CLKS_NR_PERIC0	(CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK + 1)

#define CLKS_NR_PERIC1	(CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK + 1)



/* ---- CMU_TOP ------------------------------------------------------------- */
@@ -3066,6 +3067,348 @@ static const struct samsung_cmu_info peric0_cmu_info __initconst = { 
	.clk_name		= "bus",

};



/* ---- CMU_PERIC1 ---------------------------------------------------------- */



/* Register Offset definitions for CMU_PERIC1 (0x10c00000) */

#define PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER						0x0600

#define PLL_CON1_MUX_CLKCMU_PERIC1_BUS_USER						0x0604

#define PLL_CON0_MUX_CLKCMU_PERIC1_I3C_USER						0x0610

#define PLL_CON1_MUX_CLKCMU_PERIC1_I3C_USER						0x0614

#define PLL_CON0_MUX_CLKCMU_PERIC1_USI0_USI_USER					0x0620

#define PLL_CON1_MUX_CLKCMU_PERIC1_USI0_USI_USER					0x0624

#define PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER					0x0630

#define PLL_CON1_MUX_CLKCMU_PERIC1_USI10_USI_USER					0x0634

#define PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER					0x0640

#define PLL_CON1_MUX_CLKCMU_PERIC1_USI11_USI_USER					0x0644

#define PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER					0x0650

#define PLL_CON1_MUX_CLKCMU_PERIC1_USI12_USI_USER					0x0654

#define PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USI_USER					0x0660

#define PLL_CON1_MUX_CLKCMU_PERIC1_USI13_USI_USER					0x0664

#define PLL_CON0_MUX_CLKCMU_PERIC1_USI9_USI_USER					0x0670

#define PLL_CON1_MUX_CLKCMU_PERIC1_USI9_USI_USER					0x0674

#define PERIC1_CMU_PERIC1_CONTROLLER_OPTION						0x0800

#define CLKOUT_CON_BLK_PERIC1_CMU_PERIC1_CLKOUT0					0x0810

#define CLK_CON_DIV_DIV_CLK_PERIC1_I3C							0x1800

#define CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI						0x1804

#define CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI						0x1808

#define CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI						0x180c

#define CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI						0x1810

#define CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI						0x1814

#define CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI						0x1818

#define CLK_CON_BUF_CLKBUF_PERIC1_IP							0x2000

#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK			0x2004

#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I3C_IPCLKPORT_CLK		0x2008

#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK		0x200c

#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK			0x2010

#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPC_PERIC1_IPCLKPORT_PCLK			0x2014

#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK			0x2018

#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK		0x201c

#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1			0x2020

#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2			0x2024

#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3			0x2028

#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4			0x202c

#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5			0x2030

#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6			0x2034

#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8			0x2038

#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1			0x203c

#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_15			0x2040

#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2			0x2044

#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3			0x2048

#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4			0x204c

#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5			0x2050

#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6			0x2054

#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8			0x2058

#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK		0x205c

#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI0_USI_IPCLKPORT_CLK	0x2060

#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK	0x2064

#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK	0x2068

#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK	0x206c

#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI13_USI_IPCLKPORT_CLK	0x2070

#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI9_USI_IPCLKPORT_CLK	0x2074

#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK			0x2078

#define DMYQCH_CON_PERIC1_TOP0_QCH_S							0x3000

#define PCH_CON_LHM_AXI_P_PERIC1_PCH							0x3004

#define QCH_CON_D_TZPC_PERIC1_QCH							0x3008

#define QCH_CON_GPC_PERIC1_QCH								0x300c

#define QCH_CON_GPIO_PERIC1_QCH								0x3010

#define QCH_CON_LHM_AXI_P_PERIC1_QCH							0x3014

#define QCH_CON_PERIC1_CMU_PERIC1_QCH							0x3018

#define QCH_CON_PERIC1_TOP0_QCH_I3C0							0x301c

#define QCH_CON_PERIC1_TOP0_QCH_PWM							0x3020

#define QCH_CON_PERIC1_TOP0_QCH_USI0_USI						0x3024

#define QCH_CON_PERIC1_TOP0_QCH_USI10_USI						0x3028

#define QCH_CON_PERIC1_TOP0_QCH_USI11_USI						0x302c

#define QCH_CON_PERIC1_TOP0_QCH_USI12_USI						0x3030

#define QCH_CON_PERIC1_TOP0_QCH_USI13_USI						0x3034

#define QCH_CON_PERIC1_TOP0_QCH_USI9_USI						0x3038

#define QCH_CON_SYSREG_PERIC1_QCH							0x303c

#define QUEUE_CTRL_REG_BLK_PERIC1_CMU_PERIC1						0x3c00



static const unsigned long peric1_clk_regs[] __initconst = {

	PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER,

	PLL_CON1_MUX_CLKCMU_PERIC1_BUS_USER,

	PLL_CON0_MUX_CLKCMU_PERIC1_I3C_USER,

	PLL_CON1_MUX_CLKCMU_PERIC1_I3C_USER,

	PLL_CON0_MUX_CLKCMU_PERIC1_USI0_USI_USER,

	PLL_CON1_MUX_CLKCMU_PERIC1_USI0_USI_USER,

	PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER,

	PLL_CON1_MUX_CLKCMU_PERIC1_USI10_USI_USER,

	PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER,

	PLL_CON1_MUX_CLKCMU_PERIC1_USI11_USI_USER,

	PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER,

	PLL_CON1_MUX_CLKCMU_PERIC1_USI12_USI_USER,

	PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USI_USER,

	PLL_CON1_MUX_CLKCMU_PERIC1_USI13_USI_USER,

	PLL_CON0_MUX_CLKCMU_PERIC1_USI9_USI_USER,

	PLL_CON1_MUX_CLKCMU_PERIC1_USI9_USI_USER,

	PERIC1_CMU_PERIC1_CONTROLLER_OPTION,

	CLKOUT_CON_BLK_PERIC1_CMU_PERIC1_CLKOUT0,

	CLK_CON_DIV_DIV_CLK_PERIC1_I3C,

	CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI,

	CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI,

	CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI,

	CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI,

	CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI,

	CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI,

	CLK_CON_BUF_CLKBUF_PERIC1_IP,

	CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK,

	CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I3C_IPCLKPORT_CLK,

	CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK,

	CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK,

	CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPC_PERIC1_IPCLKPORT_PCLK,

	CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK,

	CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK,

	CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1,

	CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2,

	CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3,

	CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4,

	CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5,

	CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6,

	CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8,

	CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1,

	CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_15,

	CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2,

	CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3,

	CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4,

	CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5,

	CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6,

	CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8,

	CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK,

	CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI0_USI_IPCLKPORT_CLK,

	CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK,

	CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK,

	CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK,

	CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI13_USI_IPCLKPORT_CLK,

	CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI9_USI_IPCLKPORT_CLK,

	CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK,

	DMYQCH_CON_PERIC1_TOP0_QCH_S,

	PCH_CON_LHM_AXI_P_PERIC1_PCH,

	QCH_CON_D_TZPC_PERIC1_QCH,

	QCH_CON_GPC_PERIC1_QCH,

	QCH_CON_GPIO_PERIC1_QCH,

	QCH_CON_LHM_AXI_P_PERIC1_QCH,

	QCH_CON_PERIC1_CMU_PERIC1_QCH,

	QCH_CON_PERIC1_TOP0_QCH_I3C0,

	QCH_CON_PERIC1_TOP0_QCH_PWM,

	QCH_CON_PERIC1_TOP0_QCH_USI0_USI,

	QCH_CON_PERIC1_TOP0_QCH_USI10_USI,

	QCH_CON_PERIC1_TOP0_QCH_USI11_USI,

	QCH_CON_PERIC1_TOP0_QCH_USI12_USI,

	QCH_CON_PERIC1_TOP0_QCH_USI13_USI,

	QCH_CON_PERIC1_TOP0_QCH_USI9_USI,

	QCH_CON_SYSREG_PERIC1_QCH,

	QUEUE_CTRL_REG_BLK_PERIC1_CMU_PERIC1,

};



/* List of parent clocks for Muxes in CMU_PERIC1 */

PNAME(mout_peric1_bus_user_p)		= { "oscclk", "dout_cmu_peric1_bus" };

PNAME(mout_peric1_nonbususer_p)		= { "oscclk", "dout_cmu_peric1_ip" };



static const struct samsung_mux_clock peric1_mux_clks[] __initconst = {

	MUX(CLK_MOUT_PERIC1_BUS_USER, "mout_peric1_bus_user",

	    mout_peric1_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER, 4, 1),

	MUX(CLK_MOUT_PERIC1_I3C_USER,

	    "mout_peric1_i3c_user", mout_peric1_nonbususer_p,

	    PLL_CON0_MUX_CLKCMU_PERIC1_I3C_USER, 4, 1),

	MUX(CLK_MOUT_PERIC1_USI0_USI_USER,

	    "mout_peric1_usi0_usi_user", mout_peric1_nonbususer_p,

	    PLL_CON0_MUX_CLKCMU_PERIC1_USI0_USI_USER, 4, 1),

	MUX(CLK_MOUT_PERIC1_USI10_USI_USER,

	    "mout_peric1_usi10_usi_user", mout_peric1_nonbususer_p,

	    PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER, 4, 1),

	MUX(CLK_MOUT_PERIC1_USI11_USI_USER,

	    "mout_peric1_usi11_usi_user", mout_peric1_nonbususer_p,

	    PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER, 4, 1),

	MUX(CLK_MOUT_PERIC1_USI12_USI_USER,

	    "mout_peric1_usi12_usi_user", mout_peric1_nonbususer_p,

	    PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER, 4, 1),

	MUX(CLK_MOUT_PERIC1_USI13_USI_USER,

	    "mout_peric1_usi13_usi_user", mout_peric1_nonbususer_p,

	    PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USI_USER, 4, 1),

	MUX(CLK_MOUT_PERIC1_USI9_USI_USER,

	    "mout_peric1_usi9_usi_user", mout_peric1_nonbususer_p,

	    PLL_CON0_MUX_CLKCMU_PERIC1_USI9_USI_USER, 4, 1),

};



static const struct samsung_div_clock peric1_div_clks[] __initconst = {

	DIV(CLK_DOUT_PERIC1_I3C, "dout_peric1_i3c", "mout_peric1_i3c_user",

	    CLK_CON_DIV_DIV_CLK_PERIC1_I3C, 0, 4),

	DIV(CLK_DOUT_PERIC1_USI0_USI,

	    "dout_peric1_usi0_usi", "mout_peric1_usi0_usi_user",

	    CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI, 0, 4),

	DIV(CLK_DOUT_PERIC1_USI10_USI,

	    "dout_peric1_usi10_usi", "mout_peric1_usi10_usi_user",

	    CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI, 0, 4),

	DIV(CLK_DOUT_PERIC1_USI11_USI,

	    "dout_peric1_usi11_usi", "mout_peric1_usi11_usi_user",

	    CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI, 0, 4),

	DIV(CLK_DOUT_PERIC1_USI12_USI,

	    "dout_peric1_usi12_usi", "mout_peric1_usi12_usi_user",

	    CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI, 0, 4),

	DIV(CLK_DOUT_PERIC1_USI13_USI,

	    "dout_peric1_usi13_usi", "mout_peric1_usi13_usi_user",

	    CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI, 0, 4),

	DIV(CLK_DOUT_PERIC1_USI9_USI,

	    "dout_peric1_usi9_usi", "mout_peric1_usi9_usi_user",

	    CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI, 0, 4),

};



static const struct samsung_gate_clock peric1_gate_clks[] __initconst = {

	GATE(CLK_GOUT_PERIC1_PCLK,

	     "gout_peric1_peric1_pclk", "mout_peric1_bus_user",

	     CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK,

	     21, CLK_IS_CRITICAL, 0),

	GATE(CLK_GOUT_PERIC1_CLK_PERIC1_I3C_CLK,

	     "gout_peric1_clk_peric1_i3c_clk", "dout_peric1_i3c",

	     CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I3C_IPCLKPORT_CLK,

	     21, 0, 0),

	GATE(CLK_GOUT_PERIC1_CLK_PERIC1_OSCCLK_CLK,

	     "gout_peric1_clk_peric1_oscclk_clk", "oscclk",

	     CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK,

	     21, 0, 0),

	GATE(CLK_GOUT_PERIC1_D_TZPC_PERIC1_PCLK,

	     "gout_peric1_d_tzpc_peric1_pclk", "mout_peric1_bus_user",

	     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK,

	     21, 0, 0),

	GATE(CLK_GOUT_PERIC1_GPC_PERIC1_PCLK,

	     "gout_peric1_gpc_peric1_pclk", "mout_peric1_bus_user",

	     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPC_PERIC1_IPCLKPORT_PCLK,

	     21, 0, 0),

	GATE(CLK_GOUT_PERIC1_GPIO_PERIC1_PCLK,

	     "gout_peric1_gpio_peric1_pclk", "mout_peric1_bus_user",

	     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK,

	     21, CLK_IGNORE_UNUSED, 0),

	GATE(CLK_GOUT_PERIC1_LHM_AXI_P_PERIC1_I_CLK,

	     "gout_peric1_lhm_axi_p_peric1_i_clk", "mout_peric1_bus_user",

	     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK,

	     21, CLK_IS_CRITICAL, 0),

	GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1,

	     "gout_peric1_peric1_top0_ipclk_1", "dout_peric1_usi0_usi",

	     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1,

	     21, 0, 0),

	GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2,

	     "gout_peric1_peric1_top0_ipclk_2", "dout_peric1_usi9_usi",

	     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2,

	     21, 0, 0),

	GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3,

	     "gout_peric1_peric1_top0_ipclk_3", "dout_peric1_usi10_usi",

	     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3,

	     21, 0, 0),

	GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4,

	     "gout_peric1_peric1_top0_ipclk_4", "dout_peric1_usi11_usi",

	     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4,

	     21, 0, 0),

	GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5,

	     "gout_peric1_peric1_top0_ipclk_5", "dout_peric1_usi12_usi",

	     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5,

	     21, 0, 0),

	GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6,

	     "gout_peric1_peric1_top0_ipclk_6", "dout_peric1_usi13_usi",

	     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6,

	     21, 0, 0),

	GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_8,

	     "gout_peric1_peric1_top0_ipclk_8", "dout_peric1_i3c",

	     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8,

	     21, 0, 0),

	GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1,

	     "gout_peric1_peric1_top0_pclk_1", "mout_peric1_bus_user",

	     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1,

	     21, 0, 0),

	GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_15,

	     "gout_peric1_peric1_top0_pclk_15", "mout_peric1_bus_user",

	     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_15,

	     21, 0, 0),

	GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2,

	     "gout_peric1_peric1_top0_pclk_2", "mout_peric1_bus_user",

	     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2,

	     21, 0, 0),

	GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3,

	     "gout_peric1_peric1_top0_pclk_3", "mout_peric1_bus_user",

	     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3,

	     21, 0, 0),

	GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4,

	     "gout_peric1_peric1_top0_pclk_4", "mout_peric1_bus_user",

	     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4,

	     21, 0, 0),

	GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5,

	     "gout_peric1_peric1_top0_pclk_5", "mout_peric1_bus_user",

	     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5,

	     21, 0, 0),

	GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6,

	     "gout_peric1_peric1_top0_pclk_6", "mout_peric1_bus_user",

	     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6,

	     21, 0, 0),

	GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_8,

	     "gout_peric1_peric1_top0_pclk_8", "mout_peric1_bus_user",

	     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8,

	     21, 0, 0),

	GATE(CLK_GOUT_PERIC1_CLK_PERIC1_BUSP_CLK,

	     "gout_peric1_clk_peric1_busp_clk", "mout_peric1_bus_user",

	     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK,

	     21, 0, 0),

	GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI0_USI_CLK,

	     "gout_peric1_clk_peric1_usi0_usi_clk", "dout_peric1_usi0_usi",

	     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI0_USI_IPCLKPORT_CLK,

	     21, 0, 0),

	GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI10_USI_CLK,

	     "gout_peric1_clk_peric1_usi10_usi_clk", "dout_peric1_usi10_usi",

	     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK,

	     21, 0, 0),

	GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI11_USI_CLK,

	     "gout_peric1_clk_peric1_usi11_usi_clk", "dout_peric1_usi11_usi",

	     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK,

	     21, 0, 0),

	GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI12_USI_CLK,

	     "gout_peric1_clk_peric1_usi12_usi_clk", "dout_peric1_usi12_usi",

	     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK,

	     21, 0, 0),

	GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI13_USI_CLK,

	     "gout_peric1_clk_peric1_usi13_usi_clk", "dout_peric1_usi13_usi",

	     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI13_USI_IPCLKPORT_CLK,

	     21, 0, 0),

	GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI9_USI_CLK,

	     "gout_peric1_clk_peric1_usi9_usi_clk", "dout_peric1_usi9_usi",

	     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI9_USI_IPCLKPORT_CLK,

	     21, 0, 0),

	GATE(CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK,

	     "gout_peric1_sysreg_peric1_pclk", "mout_peric1_bus_user",

	     CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK,

	     21, 0, 0),

};



static const struct samsung_cmu_info peric1_cmu_info __initconst = {

	.mux_clks		= peric1_mux_clks,

	.nr_mux_clks		= ARRAY_SIZE(peric1_mux_clks),

	.div_clks		= peric1_div_clks,

	.nr_div_clks		= ARRAY_SIZE(peric1_div_clks),

	.gate_clks		= peric1_gate_clks,

	.nr_gate_clks		= ARRAY_SIZE(peric1_gate_clks),

	.nr_clk_ids		= CLKS_NR_PERIC1,

	.clk_regs		= peric1_clk_regs,

	.nr_clk_regs		= ARRAY_SIZE(peric1_clk_regs),

	.clk_name		= "bus",

};



/* ---- platform_driver ----------------------------------------------------- */



static int __init gs101_cmu_probe(struct platform_device *pdev)
@@ -3086,6 +3429,9 @@ static const struct of_device_id gs101_cmu_of_match[] = { 
	}, {

		.compatible = "google,gs101-cmu-peric0",

		.data = &peric0_cmu_info,

	}, {

		.compatible = "google,gs101-cmu-peric1",

		.data = &peric1_cmu_info,

	}, {

	},

};