Loading arch/arm/mach-pxa/generic.c +0 −13 Original line number Diff line number Diff line Loading @@ -71,19 +71,6 @@ unsigned int get_clk_frequency_khz(int info) } EXPORT_SYMBOL(get_clk_frequency_khz); /* * Return the current memory clock frequency in units of 10kHz */ unsigned int get_memclk_frequency_10khz(void) { if (cpu_is_pxa25x()) return pxa25x_get_memclk_frequency_10khz(); else if (cpu_is_pxa27x()) return pxa27x_get_memclk_frequency_10khz(); return 0; } EXPORT_SYMBOL(get_memclk_frequency_10khz); /* * Intel PXA2xx internal register mapping. * Loading arch/arm/mach-pxa/generic.h +0 −4 Original line number Diff line number Diff line Loading @@ -36,18 +36,14 @@ extern unsigned int get_clk_frequency_khz(int info); #ifdef CONFIG_PXA25x extern unsigned pxa25x_get_clk_frequency_khz(int); extern unsigned pxa25x_get_memclk_frequency_10khz(void); #else #define pxa25x_get_clk_frequency_khz(x) (0) #define pxa25x_get_memclk_frequency_10khz() (0) #endif #ifdef CONFIG_PXA27x extern unsigned pxa27x_get_clk_frequency_khz(int); extern unsigned pxa27x_get_memclk_frequency_10khz(void); #else #define pxa27x_get_clk_frequency_khz(x) (0) #define pxa27x_get_memclk_frequency_10khz() (0) #endif #if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x) Loading arch/arm/mach-pxa/pxa25x.c +10 −10 Original line number Diff line number Diff line Loading @@ -92,23 +92,21 @@ unsigned int pxa25x_get_clk_frequency_khz(int info) return (turbo & 1) ? (N/1000) : (M/1000); } /* * Return the current memory clock frequency in units of 10kHz */ unsigned int pxa25x_get_memclk_frequency_10khz(void) static unsigned long clk_pxa25x_mem_getrate(struct clk *clk) { return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK / 10000; return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK; } static unsigned long clk_pxa25x_lcd_getrate(struct clk *clk) { return pxa25x_get_memclk_frequency_10khz() * 10000; } static const struct clkops clk_pxa25x_mem_ops = { .enable = clk_dummy_enable, .disable = clk_dummy_disable, .getrate = clk_pxa25x_mem_getrate, }; static const struct clkops clk_pxa25x_lcd_ops = { .enable = clk_pxa2xx_cken_enable, .disable = clk_pxa2xx_cken_disable, .getrate = clk_pxa25x_lcd_getrate, .getrate = clk_pxa25x_mem_getrate, }; static unsigned long gpio12_config_32k[] = { Loading Loading @@ -185,6 +183,7 @@ static DEFINE_PXA2_CKEN(pxa25x_ficp, FICP, 47923000, 0); static DEFINE_CK(pxa25x_lcd, LCD, &clk_pxa25x_lcd_ops); static DEFINE_CLK(pxa25x_gpio11, &clk_pxa25x_gpio11_ops, 3686400, 0); static DEFINE_CLK(pxa25x_gpio12, &clk_pxa25x_gpio12_ops, 32768, 0); static DEFINE_CLK(pxa25x_mem, &clk_pxa25x_mem_ops, 0, 0); static struct clk_lookup pxa25x_clkregs[] = { INIT_CLKREG(&clk_pxa25x_lcd, "pxa2xx-fb", NULL), Loading @@ -205,6 +204,7 @@ static struct clk_lookup pxa25x_clkregs[] = { INIT_CLKREG(&clk_pxa25x_ac97, NULL, "AC97CLK"), INIT_CLKREG(&clk_pxa25x_gpio11, NULL, "GPIO11_CLK"), INIT_CLKREG(&clk_pxa25x_gpio12, NULL, "GPIO12_CLK"), INIT_CLKREG(&clk_pxa25x_mem, "pxa2xx-pcmcia", NULL), }; static struct clk_lookup pxa25x_hwuart_clkreg = Loading arch/arm/mach-pxa/pxa27x.c +11 −4 Original line number Diff line number Diff line Loading @@ -111,10 +111,9 @@ unsigned int pxa27x_get_clk_frequency_khz(int info) } /* * Return the current mem clock frequency in units of 10kHz as * reflected by CCCR[A], B, and L * Return the current mem clock frequency as reflected by CCCR[A], B, and L */ unsigned int pxa27x_get_memclk_frequency_10khz(void) static unsigned long clk_pxa27x_mem_getrate(struct clk *clk) { unsigned long ccsr, clkcfg; unsigned int l, L, m, M; Loading @@ -133,9 +132,15 @@ unsigned int pxa27x_get_memclk_frequency_10khz(void) L = l * BASE_CLK; M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2)); return (M / 10000); return M; } static const struct clkops clk_pxa27x_mem_ops = { .enable = clk_dummy_enable, .disable = clk_dummy_disable, .getrate = clk_pxa27x_mem_getrate, }; /* * Return the current LCD clock frequency in units of 10kHz as */ Loading Loading @@ -192,6 +197,7 @@ static DEFINE_PXA2_CKEN(pxa27x_memc, MEMC, 0, 0); static DEFINE_CK(pxa27x_lcd, LCD, &clk_pxa27x_lcd_ops); static DEFINE_CK(pxa27x_camera, CAMERA, &clk_pxa27x_lcd_ops); static DEFINE_CLK(pxa27x_mem, &clk_pxa27x_mem_ops, 0, 0); static struct clk_lookup pxa27x_clkregs[] = { INIT_CLKREG(&clk_pxa27x_lcd, "pxa2xx-fb", NULL), Loading Loading @@ -220,6 +226,7 @@ static struct clk_lookup pxa27x_clkregs[] = { INIT_CLKREG(&clk_pxa27x_memstk, NULL, "MSTKCLK"), INIT_CLKREG(&clk_pxa27x_im, NULL, "IMCLK"), INIT_CLKREG(&clk_pxa27x_memc, NULL, "MEMCLK"), INIT_CLKREG(&clk_pxa27x_mem, "pxa2xx-pcmcia", NULL), }; #ifdef CONFIG_PM Loading drivers/pcmcia/pxa2xx_base.c +14 −3 Original line number Diff line number Diff line Loading @@ -179,8 +179,8 @@ static int pxa2xx_pcmcia_set_mcxx(struct soc_pcmcia_socket *skt, unsigned int cl static int pxa2xx_pcmcia_set_timing(struct soc_pcmcia_socket *skt) { unsigned int clk = get_memclk_frequency_10khz(); return pxa2xx_pcmcia_set_mcxx(skt, clk); unsigned long clk = clk_get_rate(skt->clk); return pxa2xx_pcmcia_set_mcxx(skt, clk / 10000); } #ifdef CONFIG_CPU_FREQ Loading Loading @@ -282,24 +282,33 @@ static int pxa2xx_drv_pcmcia_probe(struct platform_device *dev) struct pcmcia_low_level *ops; struct skt_dev_info *sinfo; struct soc_pcmcia_socket *skt; struct clk *clk; ops = (struct pcmcia_low_level *)dev->dev.platform_data; if (!ops) return -ENODEV; clk = clk_get(&dev->dev, NULL); if (!clk) return -ENODEV; pxa2xx_drv_pcmcia_ops(ops); sinfo = kzalloc(SKT_DEV_INFO_SIZE(ops->nr), GFP_KERNEL); if (!sinfo) if (!sinfo) { clk_put(clk); return -ENOMEM; } sinfo->nskt = ops->nr; sinfo->clk = clk; /* Initialize processor specific parameters */ for (i = 0; i < ops->nr; i++) { skt = &sinfo->skt[i]; skt->nr = ops->first + i; skt->clk = clk; skt->ops = ops; skt->socket.owner = ops->owner; skt->socket.dev.parent = &dev->dev; Loading @@ -314,6 +323,7 @@ static int pxa2xx_drv_pcmcia_probe(struct platform_device *dev) while (--i >= 0) soc_pcmcia_remove_one(&sinfo->skt[i]); kfree(sinfo); clk_put(clk); } else { pxa2xx_configure_sockets(&dev->dev); dev_set_drvdata(&dev->dev, sinfo); Loading @@ -332,6 +342,7 @@ static int pxa2xx_drv_pcmcia_remove(struct platform_device *dev) for (i = 0; i < sinfo->nskt; i++) soc_pcmcia_remove_one(&sinfo->skt[i]); clk_put(sinfo->clk); kfree(sinfo); return 0; } Loading Loading
arch/arm/mach-pxa/generic.c +0 −13 Original line number Diff line number Diff line Loading @@ -71,19 +71,6 @@ unsigned int get_clk_frequency_khz(int info) } EXPORT_SYMBOL(get_clk_frequency_khz); /* * Return the current memory clock frequency in units of 10kHz */ unsigned int get_memclk_frequency_10khz(void) { if (cpu_is_pxa25x()) return pxa25x_get_memclk_frequency_10khz(); else if (cpu_is_pxa27x()) return pxa27x_get_memclk_frequency_10khz(); return 0; } EXPORT_SYMBOL(get_memclk_frequency_10khz); /* * Intel PXA2xx internal register mapping. * Loading
arch/arm/mach-pxa/generic.h +0 −4 Original line number Diff line number Diff line Loading @@ -36,18 +36,14 @@ extern unsigned int get_clk_frequency_khz(int info); #ifdef CONFIG_PXA25x extern unsigned pxa25x_get_clk_frequency_khz(int); extern unsigned pxa25x_get_memclk_frequency_10khz(void); #else #define pxa25x_get_clk_frequency_khz(x) (0) #define pxa25x_get_memclk_frequency_10khz() (0) #endif #ifdef CONFIG_PXA27x extern unsigned pxa27x_get_clk_frequency_khz(int); extern unsigned pxa27x_get_memclk_frequency_10khz(void); #else #define pxa27x_get_clk_frequency_khz(x) (0) #define pxa27x_get_memclk_frequency_10khz() (0) #endif #if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x) Loading
arch/arm/mach-pxa/pxa25x.c +10 −10 Original line number Diff line number Diff line Loading @@ -92,23 +92,21 @@ unsigned int pxa25x_get_clk_frequency_khz(int info) return (turbo & 1) ? (N/1000) : (M/1000); } /* * Return the current memory clock frequency in units of 10kHz */ unsigned int pxa25x_get_memclk_frequency_10khz(void) static unsigned long clk_pxa25x_mem_getrate(struct clk *clk) { return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK / 10000; return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK; } static unsigned long clk_pxa25x_lcd_getrate(struct clk *clk) { return pxa25x_get_memclk_frequency_10khz() * 10000; } static const struct clkops clk_pxa25x_mem_ops = { .enable = clk_dummy_enable, .disable = clk_dummy_disable, .getrate = clk_pxa25x_mem_getrate, }; static const struct clkops clk_pxa25x_lcd_ops = { .enable = clk_pxa2xx_cken_enable, .disable = clk_pxa2xx_cken_disable, .getrate = clk_pxa25x_lcd_getrate, .getrate = clk_pxa25x_mem_getrate, }; static unsigned long gpio12_config_32k[] = { Loading Loading @@ -185,6 +183,7 @@ static DEFINE_PXA2_CKEN(pxa25x_ficp, FICP, 47923000, 0); static DEFINE_CK(pxa25x_lcd, LCD, &clk_pxa25x_lcd_ops); static DEFINE_CLK(pxa25x_gpio11, &clk_pxa25x_gpio11_ops, 3686400, 0); static DEFINE_CLK(pxa25x_gpio12, &clk_pxa25x_gpio12_ops, 32768, 0); static DEFINE_CLK(pxa25x_mem, &clk_pxa25x_mem_ops, 0, 0); static struct clk_lookup pxa25x_clkregs[] = { INIT_CLKREG(&clk_pxa25x_lcd, "pxa2xx-fb", NULL), Loading @@ -205,6 +204,7 @@ static struct clk_lookup pxa25x_clkregs[] = { INIT_CLKREG(&clk_pxa25x_ac97, NULL, "AC97CLK"), INIT_CLKREG(&clk_pxa25x_gpio11, NULL, "GPIO11_CLK"), INIT_CLKREG(&clk_pxa25x_gpio12, NULL, "GPIO12_CLK"), INIT_CLKREG(&clk_pxa25x_mem, "pxa2xx-pcmcia", NULL), }; static struct clk_lookup pxa25x_hwuart_clkreg = Loading
arch/arm/mach-pxa/pxa27x.c +11 −4 Original line number Diff line number Diff line Loading @@ -111,10 +111,9 @@ unsigned int pxa27x_get_clk_frequency_khz(int info) } /* * Return the current mem clock frequency in units of 10kHz as * reflected by CCCR[A], B, and L * Return the current mem clock frequency as reflected by CCCR[A], B, and L */ unsigned int pxa27x_get_memclk_frequency_10khz(void) static unsigned long clk_pxa27x_mem_getrate(struct clk *clk) { unsigned long ccsr, clkcfg; unsigned int l, L, m, M; Loading @@ -133,9 +132,15 @@ unsigned int pxa27x_get_memclk_frequency_10khz(void) L = l * BASE_CLK; M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2)); return (M / 10000); return M; } static const struct clkops clk_pxa27x_mem_ops = { .enable = clk_dummy_enable, .disable = clk_dummy_disable, .getrate = clk_pxa27x_mem_getrate, }; /* * Return the current LCD clock frequency in units of 10kHz as */ Loading Loading @@ -192,6 +197,7 @@ static DEFINE_PXA2_CKEN(pxa27x_memc, MEMC, 0, 0); static DEFINE_CK(pxa27x_lcd, LCD, &clk_pxa27x_lcd_ops); static DEFINE_CK(pxa27x_camera, CAMERA, &clk_pxa27x_lcd_ops); static DEFINE_CLK(pxa27x_mem, &clk_pxa27x_mem_ops, 0, 0); static struct clk_lookup pxa27x_clkregs[] = { INIT_CLKREG(&clk_pxa27x_lcd, "pxa2xx-fb", NULL), Loading Loading @@ -220,6 +226,7 @@ static struct clk_lookup pxa27x_clkregs[] = { INIT_CLKREG(&clk_pxa27x_memstk, NULL, "MSTKCLK"), INIT_CLKREG(&clk_pxa27x_im, NULL, "IMCLK"), INIT_CLKREG(&clk_pxa27x_memc, NULL, "MEMCLK"), INIT_CLKREG(&clk_pxa27x_mem, "pxa2xx-pcmcia", NULL), }; #ifdef CONFIG_PM Loading
drivers/pcmcia/pxa2xx_base.c +14 −3 Original line number Diff line number Diff line Loading @@ -179,8 +179,8 @@ static int pxa2xx_pcmcia_set_mcxx(struct soc_pcmcia_socket *skt, unsigned int cl static int pxa2xx_pcmcia_set_timing(struct soc_pcmcia_socket *skt) { unsigned int clk = get_memclk_frequency_10khz(); return pxa2xx_pcmcia_set_mcxx(skt, clk); unsigned long clk = clk_get_rate(skt->clk); return pxa2xx_pcmcia_set_mcxx(skt, clk / 10000); } #ifdef CONFIG_CPU_FREQ Loading Loading @@ -282,24 +282,33 @@ static int pxa2xx_drv_pcmcia_probe(struct platform_device *dev) struct pcmcia_low_level *ops; struct skt_dev_info *sinfo; struct soc_pcmcia_socket *skt; struct clk *clk; ops = (struct pcmcia_low_level *)dev->dev.platform_data; if (!ops) return -ENODEV; clk = clk_get(&dev->dev, NULL); if (!clk) return -ENODEV; pxa2xx_drv_pcmcia_ops(ops); sinfo = kzalloc(SKT_DEV_INFO_SIZE(ops->nr), GFP_KERNEL); if (!sinfo) if (!sinfo) { clk_put(clk); return -ENOMEM; } sinfo->nskt = ops->nr; sinfo->clk = clk; /* Initialize processor specific parameters */ for (i = 0; i < ops->nr; i++) { skt = &sinfo->skt[i]; skt->nr = ops->first + i; skt->clk = clk; skt->ops = ops; skt->socket.owner = ops->owner; skt->socket.dev.parent = &dev->dev; Loading @@ -314,6 +323,7 @@ static int pxa2xx_drv_pcmcia_probe(struct platform_device *dev) while (--i >= 0) soc_pcmcia_remove_one(&sinfo->skt[i]); kfree(sinfo); clk_put(clk); } else { pxa2xx_configure_sockets(&dev->dev); dev_set_drvdata(&dev->dev, sinfo); Loading @@ -332,6 +342,7 @@ static int pxa2xx_drv_pcmcia_remove(struct platform_device *dev) for (i = 0; i < sinfo->nskt; i++) soc_pcmcia_remove_one(&sinfo->skt[i]); clk_put(sinfo->clk); kfree(sinfo); return 0; } Loading