Commit 2a38b0ec authored by Timur Kristóf's avatar Timur Kristóf Committed by Alex Deucher
Browse files

drm/amdgpu/si_ih: Enable soft IRQ handler ring 



We are going to use the soft IRQ handler ring on GMC v6 (SI)
to process interrupts from VM faults.

Signed-off-by: default avatarTimur Kristóf <timur.kristof@gmail.com>
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent a7fa4f2d

drivers/gpu/drm/amd/amdgpu/si_ih.c

+12 −0
Original line number Diff line number Diff line
@@ -96,6 +96,9 @@ static int si_ih_irq_init(struct amdgpu_device *adev) 
	pci_set_master(adev->pdev);

	si_ih_enable_interrupts(adev);



	if (adev->irq.ih_soft.ring_size)

		adev->irq.ih_soft.enabled = true;



	return 0;

}
@@ -112,6 +115,9 @@ static u32 si_ih_get_wptr(struct amdgpu_device *adev, 


	wptr = le32_to_cpu(*ih->wptr_cpu);



	if (ih == &adev->irq.ih_soft)

		goto out;



	if (wptr & IH_RB_WPTR__RB_OVERFLOW_MASK) {

		wptr &= ~IH_RB_WPTR__RB_OVERFLOW_MASK;

		dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
@@ -127,6 +133,8 @@ static u32 si_ih_get_wptr(struct amdgpu_device *adev, 
		tmp &= ~IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK;

		WREG32(IH_RB_CNTL, tmp);

	}



out:

	return (wptr & ih->ptr_mask);

}
@@ -175,6 +183,10 @@ static int si_ih_sw_init(struct amdgpu_ip_block *ip_block) 
	if (r)

		return r;



	r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, IH_SW_RING_SIZE, true);

	if (r)

		return r;



	return amdgpu_irq_init(adev);

}