Unverified Commit 2a5cebd0 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'samsung-clk-6.17' of... 

Merge tag 'samsung-clk-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into clk-samsung

Pull Samsung SoC clk driver updates from Krzysztof Kozlowski:

 - Fixes for clock topology on Google GS101
 - Add HSI2 clk controller on ExynosAutov920
 - Minor comment fix for Exynos850 clk driver

* tag 'samsung-clk-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  clk: samsung: exynosautov920: add block hsi2 clock support
  dt-bindings: clock: exynosautov920: add hsi2 clock definitions
  dt-bindings: clock: exynosautov920: sort clock definitions
  clk: samsung: exynos850: fix a comment
  clk: samsung: gs101: fix alternate mout_hsi0_usb20_ref parent clock
  clk: samsung: gs101: fix CLK_DOUT_CMU_G3D_BUSD
parents 19272b37 2d539f31

Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml

+31 −6
Original line number Diff line number Diff line
@@ -32,23 +32,24 @@ description: | 
properties:

  compatible:

    enum:

      - samsung,exynosautov920-cmu-top

      - samsung,exynosautov920-cmu-cpucl0

      - samsung,exynosautov920-cmu-cpucl1

      - samsung,exynosautov920-cmu-cpucl2

      - samsung,exynosautov920-cmu-peric0

      - samsung,exynosautov920-cmu-peric1

      - samsung,exynosautov920-cmu-misc

      - samsung,exynosautov920-cmu-hsi0

      - samsung,exynosautov920-cmu-hsi1

      - samsung,exynosautov920-cmu-hsi2

      - samsung,exynosautov920-cmu-misc

      - samsung,exynosautov920-cmu-peric0

      - samsung,exynosautov920-cmu-peric1

      - samsung,exynosautov920-cmu-top



  clocks:

    minItems: 1

    maxItems: 4

    maxItems: 5



  clock-names:

    minItems: 1

    maxItems: 4

    maxItems: 5



  "#clock-cells":

    const: 1
@@ -201,6 +202,30 @@ allOf: 
            - const: usbdrd

            - const: mmc_card



  - if:

      properties:

        compatible:

          contains:

            const: samsung,exynosautov920-cmu-hsi2



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (38.4 MHz)

            - description: CMU_HSI2 NOC clock (from CMU_TOP)

            - description: CMU_HSI2 NOC UFS clock (from CMU_TOP)

            - description: CMU_HSI2 UFS EMBD clock (from CMU_TOP)

            - description: CMU_HSI2 ETHERNET clock (from CMU_TOP)



        clock-names:

          items:

            - const: oscclk

            - const: noc

            - const: ufs

            - const: embd

            - const: ethernet



required:

  - compatible

  - "#clock-cells"

drivers/clk/samsung/clk-exynos850.c

+1 −1
Original line number Diff line number Diff line
@@ -1360,7 +1360,7 @@ static const unsigned long cpucl1_clk_regs[] __initconst = { 
	CLK_CON_GAT_GATE_CLK_CPUCL1_CPU,

};



/* List of parent clocks for Muxes in CMU_CPUCL0 */

/* List of parent clocks for Muxes in CMU_CPUCL1 */

PNAME(mout_pll_cpucl1_p)		 = { "oscclk", "fout_cpucl1_pll" };

PNAME(mout_cpucl1_switch_user_p)	 = { "oscclk", "dout_cpucl1_switch" };

PNAME(mout_cpucl1_dbg_user_p)		 = { "oscclk", "dout_cpucl1_dbg" };

drivers/clk/samsung/clk-exynosautov920.c

+72 −0
Original line number Diff line number Diff line
@@ -26,6 +26,7 @@ 
#define CLKS_NR_MISC			(CLK_DOUT_MISC_OSC_DIV2 + 1)

#define CLKS_NR_HSI0			(CLK_DOUT_HSI0_PCIE_APB + 1)

#define CLKS_NR_HSI1			(CLK_MOUT_HSI1_USBDRD + 1)

#define CLKS_NR_HSI2			(CLK_DOUT_HSI2_ETHERNET_PTP + 1)



/* ---- CMU_TOP ------------------------------------------------------------ */
@@ -1752,6 +1753,74 @@ static const struct samsung_cmu_info hsi1_cmu_info __initconst = { 
	.clk_name		= "noc",

};



/* ---- CMU_HSI2 --------------------------------------------------------- */



/* Register Offset definitions for CMU_HSI2 (0x16b00000) */

#define PLL_LOCKTIME_PLL_ETH                    0x0

#define PLL_CON3_PLL_ETH			0x10c

#define PLL_CON0_MUX_CLKCMU_HSI2_ETHERNET_USER  0x600

#define PLL_CON0_MUX_CLKCMU_HSI2_NOC_UFS_USER   0x610

#define PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER  0x630

#define CLK_CON_MUX_MUX_CLK_HSI2_ETHERNET       0x1000

#define CLK_CON_DIV_DIV_CLK_HSI2_ETHERNET       0x1800

#define CLK_CON_DIV_DIV_CLK_HSI2_ETHERNET_PTP   0x1804



static const unsigned long hsi2_clk_regs[] __initconst = {

	PLL_LOCKTIME_PLL_ETH,

	PLL_CON3_PLL_ETH,

	PLL_CON0_MUX_CLKCMU_HSI2_ETHERNET_USER,

	PLL_CON0_MUX_CLKCMU_HSI2_NOC_UFS_USER,

	PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER,

	CLK_CON_MUX_MUX_CLK_HSI2_ETHERNET,

	CLK_CON_DIV_DIV_CLK_HSI2_ETHERNET,

	CLK_CON_DIV_DIV_CLK_HSI2_ETHERNET_PTP,

};



static const struct samsung_pll_clock hsi2_pll_clks[] __initconst = {

	/* CMU_HSI2_PLL */

	PLL(pll_531x, FOUT_PLL_ETH, "fout_pll_eth", "oscclk",

	    PLL_LOCKTIME_PLL_ETH, PLL_CON3_PLL_ETH, NULL),

};



/* List of parent clocks for Muxes in CMU_HSI2 */

PNAME(mout_clkcmu_hsi2_noc_ufs_user_p) = { "oscclk", "dout_clkcmu_hsi2_noc_ufs" };

PNAME(mout_clkcmu_hsi2_ufs_embd_user_p) = { "oscclk", "dout_clkcmu_hsi2_ufs_embd" };

PNAME(mout_hsi2_ethernet_p) = { "fout_pll_eth", "mout_clkcmu_hsi2_ethernet_user" };

PNAME(mout_clkcmu_hsi2_ethernet_user_p) = { "oscclk", "dout_clkcmu_hsi2_ethernet" };



static const struct samsung_mux_clock hsi2_mux_clks[] __initconst = {

	MUX(CLK_MOUT_HSI2_NOC_UFS_USER, "mout_clkcmu_hsi2_noc_ufs_user",

	    mout_clkcmu_hsi2_noc_ufs_user_p, PLL_CON0_MUX_CLKCMU_HSI2_NOC_UFS_USER, 4, 1),

	MUX(CLK_MOUT_HSI2_UFS_EMBD_USER, "mout_clkcmu_hsi2_ufs_embd_user",

	    mout_clkcmu_hsi2_ufs_embd_user_p, PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER, 4, 1),

	MUX(CLK_MOUT_HSI2_ETHERNET, "mout_hsi2_ethernet",

	    mout_hsi2_ethernet_p, CLK_CON_MUX_MUX_CLK_HSI2_ETHERNET, 0, 1),

	MUX(CLK_MOUT_HSI2_ETHERNET_USER, "mout_clkcmu_hsi2_ethernet_user",

	    mout_clkcmu_hsi2_ethernet_user_p, PLL_CON0_MUX_CLKCMU_HSI2_ETHERNET_USER, 4, 1),

};



static const struct samsung_div_clock hsi2_div_clks[] __initconst = {

	DIV(CLK_DOUT_HSI2_ETHERNET, "dout_hsi2_ethernet",

	    "mout_hsi2_ethernet", CLK_CON_DIV_DIV_CLK_HSI2_ETHERNET,

	    0, 4),

	DIV(CLK_DOUT_HSI2_ETHERNET_PTP, "dout_hsi2_ethernet_ptp",

	    "mout_hsi2_ethernet", CLK_CON_DIV_DIV_CLK_HSI2_ETHERNET_PTP,

	    0, 4),

};



static const struct samsung_cmu_info hsi2_cmu_info __initconst = {

	.pll_clks               = hsi2_pll_clks,

	.nr_pll_clks            = ARRAY_SIZE(hsi2_pll_clks),

	.mux_clks               = hsi2_mux_clks,

	.nr_mux_clks            = ARRAY_SIZE(hsi2_mux_clks),

	.div_clks               = hsi2_div_clks,

	.nr_div_clks            = ARRAY_SIZE(hsi2_div_clks),

	.nr_clk_ids             = CLKS_NR_HSI2,

	.clk_regs               = hsi2_clk_regs,

	.nr_clk_regs            = ARRAY_SIZE(hsi2_clk_regs),

	.clk_name               = "noc",

};



static int __init exynosautov920_cmu_probe(struct platform_device *pdev)

{

	const struct samsung_cmu_info *info;
@@ -1779,6 +1848,9 @@ static const struct of_device_id exynosautov920_cmu_of_match[] = { 
	}, {

		.compatible = "samsung,exynosautov920-cmu-hsi1",

		.data = &hsi1_cmu_info,

	}, {

		.compatible = "samsung,exynosautov920-cmu-hsi2",

		.data = &hsi2_cmu_info,

	},

	{ }

};

drivers/clk/samsung/clk-gs101.c

+2 −2
Original line number Diff line number Diff line
@@ -1154,7 +1154,7 @@ static const struct samsung_div_clock cmu_top_div_clks[] __initconst = { 
	    CLK_CON_DIV_CLKCMU_G2D_MSCL, 0, 4),

	DIV(CLK_DOUT_CMU_G3AA_G3AA, "dout_cmu_g3aa_g3aa", "gout_cmu_g3aa_g3aa",

	    CLK_CON_DIV_CLKCMU_G3AA_G3AA, 0, 4),

	DIV(CLK_DOUT_CMU_G3D_SWITCH, "dout_cmu_g3d_busd", "gout_cmu_g3d_busd",

	DIV(CLK_DOUT_CMU_G3D_BUSD, "dout_cmu_g3d_busd", "gout_cmu_g3d_busd",

	    CLK_CON_DIV_CLKCMU_G3D_BUSD, 0, 4),

	DIV(CLK_DOUT_CMU_G3D_GLB, "dout_cmu_g3d_glb", "gout_cmu_g3d_glb",

	    CLK_CON_DIV_CLKCMU_G3D_GLB, 0, 4),
@@ -2129,7 +2129,7 @@ PNAME(mout_hsi0_usbdpdbg_user_p) = { "oscclk", 
					    "dout_cmu_hsi0_usbdpdbg" };

PNAME(mout_hsi0_bus_p)			= { "mout_hsi0_bus_user",

					    "mout_hsi0_alt_user" };

PNAME(mout_hsi0_usb20_ref_p)		= { "fout_usb_pll",

PNAME(mout_hsi0_usb20_ref_p)		= { "mout_pll_usb",

					    "mout_hsi0_tcxo_user" };

PNAME(mout_hsi0_usb31drd_p)		= { "fout_usb_pll",

					    "mout_hsi0_usb31drd_user",

include/dt-bindings/clock/samsung,exynosautov920.h

+9 −0
Original line number Diff line number Diff line
@@ -286,4 +286,13 @@ 
#define CLK_MOUT_HSI1_USBDRD_USER	3

#define CLK_MOUT_HSI1_USBDRD		4



/* CMU_HSI2 */

#define FOUT_PLL_ETH                    1

#define CLK_MOUT_HSI2_NOC_UFS_USER      2

#define CLK_MOUT_HSI2_UFS_EMBD_USER     3

#define CLK_MOUT_HSI2_ETHERNET          4

#define CLK_MOUT_HSI2_ETHERNET_USER     5

#define CLK_DOUT_HSI2_ETHERNET          6

#define CLK_DOUT_HSI2_ETHERNET_PTP      7



#endif /* _DT_BINDINGS_CLOCK_EXYNOSAUTOV920_H */