Commit 2b17a6ee authored by Uwe Kleine-König's avatar Uwe Kleine-König
Browse files

Merge tag 'ib-mfd-counter-v5.11' of... 

Merge tag 'ib-mfd-counter-v5.11' of https://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd into HEAD

Immutable branch between MFD and Counter due for the v5.11 merge window
parents 30122ce2 304d02aa

drivers/counter/stm32-timer-cnt.c

+2 −2
Original line number Diff line number Diff line
@@ -465,7 +465,7 @@ static int stm32_count_events_configure(struct counter_device *counter) 
			ret = stm32_count_capture_configure(counter, event_node->channel, true);

			if (ret)

				return ret;

			dier |= TIM_DIER_CC_IE(event_node->channel);

			dier |= TIM_DIER_CCxIE(event_node->channel + 1);

			break;

		default:

			/* should never reach this path */
@@ -478,7 +478,7 @@ static int stm32_count_events_configure(struct counter_device *counter) 


	/* check for disabled capture events */

	for (i = 0 ; i < priv->nchannels; i++) {

		if (!(dier & TIM_DIER_CC_IE(i))) {

		if (!(dier & TIM_DIER_CCxIE(i + 1))) {

			ret = stm32_count_capture_configure(counter, i, false);

			if (ret)

				return ret;

include/linux/mfd/stm32-timers.h

+94 −85
Original line number Diff line number Diff line
@@ -24,10 +24,11 @@ 
#define TIM_CNT		0x24			/* Counter				*/

#define TIM_PSC		0x28			/* Prescaler				*/

#define TIM_ARR		0x2c			/* Auto-Reload Register			*/

#define TIM_CCR1	0x34	/* Capt/Comp Register 1    */

#define TIM_CCR2	0x38	/* Capt/Comp Register 2    */

#define TIM_CCR3	0x3C	/* Capt/Comp Register 3    */

#define TIM_CCR4	0x40	/* Capt/Comp Register 4    */

#define TIM_CCRx(x)	(0x34 + 4 * ((x) - 1))	/* Capt/Comp Register x (x ∈ {1, .. 4})	*/

#define TIM_CCR1	TIM_CCRx(1)		/* Capt/Comp Register 1			*/

#define TIM_CCR2	TIM_CCRx(2)		/* Capt/Comp Register 2			*/

#define TIM_CCR3	TIM_CCRx(3)		/* Capt/Comp Register 3			*/

#define TIM_CCR4	TIM_CCRx(4)		/* Capt/Comp Register 4			*/

#define TIM_BDTR	0x44			/* Break and Dead-Time Reg		*/

#define TIM_DCR		0x48			/* DMA control register			*/

#define TIM_DMAR	0x4C			/* DMA register for transfer		*/
@@ -41,16 +42,17 @@ 
#define TIM_SMCR_SMS		(BIT(0) | BIT(1) | BIT(2))		/* Slave mode selection				*/

#define TIM_SMCR_TS		(BIT(4) | BIT(5) | BIT(6))		/* Trigger selection				*/

#define TIM_DIER_UIE		BIT(0)					/* Update interrupt				*/

#define TIM_DIER_CC1IE	BIT(1)  /* CC1 Interrupt Enable    */

#define TIM_DIER_CC2IE	BIT(2)  /* CC2 Interrupt Enable    */

#define TIM_DIER_CC3IE	BIT(3)  /* CC3 Interrupt Enable    */

#define TIM_DIER_CC4IE	BIT(4)  /* CC4 Interrupt Enable    */

#define TIM_DIER_CC_IE(x)	BIT((x) + 1) /* CC1, CC2, CC3, CC4 interrupt enable */

#define TIM_DIER_CCxIE(x)	BIT(1 + ((x) - 1))			/* CCx Interrupt Enable	(x ∈ {1, .. 4})		*/

#define TIM_DIER_CC1IE		TIM_DIER_CCxIE(1)			/* CC1 Interrupt Enable				*/

#define TIM_DIER_CC2IE		TIM_DIER_CCxIE(2)			/* CC2 Interrupt Enable				*/

#define TIM_DIER_CC3IE		TIM_DIER_CCxIE(3)			/* CC3 Interrupt Enable				*/

#define TIM_DIER_CC4IE		TIM_DIER_CCxIE(4)			/* CC4 Interrupt Enable				*/

#define TIM_DIER_UDE		BIT(8)					/* Update DMA request Enable			*/

#define TIM_DIER_CC1DE	BIT(9)  /* CC1 DMA request Enable  */

#define TIM_DIER_CC2DE	BIT(10) /* CC2 DMA request Enable  */

#define TIM_DIER_CC3DE	BIT(11) /* CC3 DMA request Enable  */

#define TIM_DIER_CC4DE	BIT(12) /* CC4 DMA request Enable  */

#define TIM_DIER_CCxDE(x)	BIT(9 + ((x) - 1))			/* CCx DMA request Enable (x ∈ {1, .. 4})	*/

#define TIM_DIER_CC1DE		TIM_DIER_CCxDE(1)			/* CC1 DMA request Enable			*/

#define TIM_DIER_CC2DE		TIM_DIER_CCxDE(2)			/* CC2 DMA request Enable			*/

#define TIM_DIER_CC3DE		TIM_DIER_CCxDE(3)			/* CC3 DMA request Enable			*/

#define TIM_DIER_CC4DE		TIM_DIER_CCxDE(4)			/* CC4 DMA request Enable			*/

#define TIM_DIER_COMDE		BIT(13)					/* COM DMA request Enable			*/

#define TIM_DIER_TDE		BIT(14)					/* Trigger DMA request Enable			*/

#define TIM_SR_UIF		BIT(0)					/* Update interrupt flag			*/
@@ -70,19 +72,26 @@ 
#define TIM_CCMR_CC4S		(BIT(8) | BIT(9))			/* Capture/compare 4 sel			*/

#define TIM_CCMR_CC3S_TI3	BIT(0)					/* IC3 selects TI3				*/

#define TIM_CCMR_CC4S_TI4	BIT(8)					/* IC4 selects TI4				*/

#define TIM_CCER_CC1E	BIT(0)	/* Capt/Comp 1  out Ena    */

#define TIM_CCER_CC1P	BIT(1)	/* Capt/Comp 1  Polarity   */

#define TIM_CCER_CC1NE	BIT(2)	/* Capt/Comp 1N out Ena    */

#define TIM_CCER_CC1NP	BIT(3)	/* Capt/Comp 1N Polarity   */

#define TIM_CCER_CC2E	BIT(4)	/* Capt/Comp 2  out Ena    */

#define TIM_CCER_CC2P	BIT(5)	/* Capt/Comp 2  Polarity   */

#define TIM_CCER_CC2NP	BIT(7)	/* Capt/Comp 2N Polarity   */

#define TIM_CCER_CC3E	BIT(8)	/* Capt/Comp 3  out Ena    */

#define TIM_CCER_CC3P	BIT(9)	/* Capt/Comp 3  Polarity   */

#define TIM_CCER_CC3NP	BIT(11)	/* Capt/Comp 3N Polarity   */

#define TIM_CCER_CC4E	BIT(12)	/* Capt/Comp 4  out Ena    */

#define TIM_CCER_CC4P	BIT(13)	/* Capt/Comp 4  Polarity   */

#define TIM_CCER_CC4NP	BIT(15)	/* Capt/Comp 4N Polarity   */

#define TIM_CCER_CCxE(x)	BIT(0 + 4 * ((x) - 1))			/* Capt/Comp x  out Ena (x ∈ {1, .. 4})		*/

#define TIM_CCER_CCxP(x)	BIT(1 + 4 * ((x) - 1))			/* Capt/Comp x  Polarity (x ∈ {1, .. 4})	*/

#define TIM_CCER_CCxNE(x)	BIT(2 + 4 * ((x) - 1))			/* Capt/Comp xN out Ena (x ∈ {1, .. 4})		*/

#define TIM_CCER_CCxNP(x)	BIT(3 + 4 * ((x) - 1))			/* Capt/Comp xN Polarity (x ∈ {1, .. 4})	*/

#define TIM_CCER_CC1E		TIM_CCER_CCxE(1)			/* Capt/Comp 1  out Ena				*/

#define TIM_CCER_CC1P		TIM_CCER_CCxP(1)			/* Capt/Comp 1  Polarity			*/

#define TIM_CCER_CC1NE		TIM_CCER_CCxNE(1)			/* Capt/Comp 1N out Ena				*/

#define TIM_CCER_CC1NP		TIM_CCER_CCxNP(1)			/* Capt/Comp 1N Polarity			*/

#define TIM_CCER_CC2E		TIM_CCER_CCxE(2)			/* Capt/Comp 2  out Ena				*/

#define TIM_CCER_CC2P		TIM_CCER_CCxP(2)			/* Capt/Comp 2  Polarity			*/

#define TIM_CCER_CC2NE		TIM_CCER_CCxNE(2)			/* Capt/Comp 2N out Ena				*/

#define TIM_CCER_CC2NP		TIM_CCER_CCxNP(2)			/* Capt/Comp 2N Polarity			*/

#define TIM_CCER_CC3E		TIM_CCER_CCxE(3)			/* Capt/Comp 3  out Ena				*/

#define TIM_CCER_CC3P		TIM_CCER_CCxP(3)			/* Capt/Comp 3  Polarity			*/

#define TIM_CCER_CC3NE		TIM_CCER_CCxNE(3)			/* Capt/Comp 3N out Ena				*/

#define TIM_CCER_CC3NP		TIM_CCER_CCxNP(3)			/* Capt/Comp 3N Polarity			*/

#define TIM_CCER_CC4E		TIM_CCER_CCxE(4)			/* Capt/Comp 4  out Ena				*/

#define TIM_CCER_CC4P		TIM_CCER_CCxP(4)			/* Capt/Comp 4  Polarity			*/

#define TIM_CCER_CC4NE		TIM_CCER_CCxNE(4)			/* Capt/Comp 4N out Ena				*/

#define TIM_CCER_CC4NP		TIM_CCER_CCxNP(4)			/* Capt/Comp 4N Polarity			*/

#define TIM_CCER_CCXE		(BIT(0) | BIT(4) | BIT(8) | BIT(12))

#define TIM_BDTR_BKE(x)		BIT(12 + (x) * 12)			/* Break input enable				*/

#define TIM_BDTR_BKP(x)		BIT(13 + (x) * 12)			/* Break input polarity				*/