Commit 2b3f2b78 authored by Anup Patel's avatar Anup Patel Committed by Anup Patel
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KVM: riscv: selftests: Add condops extensions to get-reg-list test 



We have a new conditional operations related ISA extensions so let us
add these extensions to get-reg-list test.

Signed-off-by: default avatarAnup Patel <apatel@ventanamicro.com>
Reviewed-by: default avatarAndrew Jones <ajones@ventanamicro.com>
Signed-off-by: default avatarAnup Patel <anup@brainfault.org>
parent e1a8db0c

tools/testing/selftests/kvm/riscv/get-reg-list.c

+17 −0
Original line number Diff line number Diff line
@@ -48,6 +48,7 @@ bool filter_reg(__u64 reg) 
	case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICBOM:

	case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICBOZ:

	case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICNTR:

	case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICOND:

	case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICSR:

	case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIFENCEI:

	case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIHINTPAUSE:
@@ -361,6 +362,7 @@ static const char *isa_ext_id_to_str(__u64 id) 
		KVM_ISA_EXT_ARR(ZICBOM),

		KVM_ISA_EXT_ARR(ZICBOZ),

		KVM_ISA_EXT_ARR(ZICNTR),

		KVM_ISA_EXT_ARR(ZICOND),

		KVM_ISA_EXT_ARR(ZICSR),

		KVM_ISA_EXT_ARR(ZIFENCEI),

		KVM_ISA_EXT_ARR(ZIHINTPAUSE),
@@ -632,6 +634,10 @@ static __u64 zicntr_regs[] = { 
	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICNTR,

};



static __u64 zicond_regs[] = {

	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICOND,

};



static __u64 zicsr_regs[] = {

	KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICSR,

};
@@ -759,6 +765,8 @@ static __u64 fp_d_regs[] = { 
	{"zbs", .feature = KVM_RISCV_ISA_EXT_ZBS, .regs = zbs_regs, .regs_n = ARRAY_SIZE(zbs_regs),}

#define ZICNTR_REGS_SUBLIST \

	{"zicntr", .feature = KVM_RISCV_ISA_EXT_ZICNTR, .regs = zicntr_regs, .regs_n = ARRAY_SIZE(zicntr_regs),}

#define ZICOND_REGS_SUBLIST \

	{"zicond", .feature = KVM_RISCV_ISA_EXT_ZICOND, .regs = zicond_regs, .regs_n = ARRAY_SIZE(zicond_regs),}

#define ZICSR_REGS_SUBLIST \

	{"zicsr", .feature = KVM_RISCV_ISA_EXT_ZICSR, .regs = zicsr_regs, .regs_n = ARRAY_SIZE(zicsr_regs),}

#define ZIFENCEI_REGS_SUBLIST \
@@ -864,6 +872,14 @@ static struct vcpu_reg_list zicntr_config = { 
	},

};



static struct vcpu_reg_list zicond_config = {

	.sublists = {

	BASE_SUBLIST,

	ZICOND_REGS_SUBLIST,

	{0},

	},

};



static struct vcpu_reg_list zicsr_config = {

	.sublists = {

	BASE_SUBLIST,
@@ -932,6 +948,7 @@ struct vcpu_reg_list *vcpu_configs[] = { 
	&zbb_config,

	&zbs_config,

	&zicntr_config,

	&zicond_config,

	&zicsr_config,

	&zifencei_config,

	&zihpm_config,