Commit 2b7ced10 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux 

Pull arm64 fixes from Will Deacon:
 "The major fix here is for a filesystem corruption issue reported on
  Apple M1 as a result of buggy management of the floating point
  register state introduced in 6.8. I initially reverted one of the
  offending patches, but in the end Ard cooked a proper fix so there's a
  revert+reapply in the series.

  Aside from that, we've got some CPU errata workarounds and misc other
  fixes.

   - Fix broken FP register state tracking which resulted in filesystem
     corruption when dm-crypt is used

   - Workarounds for Arm CPU errata affecting the SSBS Spectre
     mitigation

   - Fix lockdep assertion in DMC620 memory controller PMU driver

   - Fix alignment of BUG table when CONFIG_DEBUG_BUGVERBOSE is
     disabled"

* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
  arm64/fpsimd: Avoid erroneous elide of user state reload
  Reapply "arm64: fpsimd: Implement lazy restore for kernel mode FPSIMD"
  arm64: asm-bug: Add .align 2 to the end of __BUG_ENTRY
  perf/arm-dmc620: Fix lockdep assert in ->event_init()
  Revert "arm64: fpsimd: Implement lazy restore for kernel mode FPSIMD"
  arm64: errata: Add workaround for Arm errata 3194386 and 3312417
  arm64: cputype: Add Neoverse-V3 definitions
  arm64: cputype: Add Cortex-X4 definitions
  arm64: barrier: Restore spec_bar() macro
parents 2ef32ad2 e92bee9f

Documentation/arch/arm64/silicon-errata.rst

+4 −0
Original line number Diff line number Diff line
@@ -140,6 +140,8 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-X2       | #2224489        | ARM64_ERRATUM_2224489       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-X4       | #3194386        | ARM64_ERRATUM_3194386       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-N1     | #1188873,1418040| ARM64_ERRATUM_1418040       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-N1     | #1349291        | N/A                         |
@@ -156,6 +158,8 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-V1     | #1619801        | N/A                         |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-V3     | #3312417        | ARM64_ERRATUM_3312417       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | MMU-500         | #841119,826419  | N/A                         |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | MMU-600         | #1076982,1209401| N/A                         |

arch/arm64/Kconfig

+42 −0
Original line number Diff line number Diff line
@@ -1067,6 +1067,48 @@ config ARM64_ERRATUM_3117295 


	  If unsure, say Y.



config ARM64_WORKAROUND_SPECULATIVE_SSBS

	bool



config ARM64_ERRATUM_3194386

	bool "Cortex-X4: 3194386: workaround for MSR SSBS not self-synchronizing"

	select ARM64_WORKAROUND_SPECULATIVE_SSBS

	default y

	help

	  This option adds the workaround for ARM Cortex-X4 erratum 3194386.



	  On affected cores "MSR SSBS, #0" instructions may not affect

	  subsequent speculative instructions, which may permit unexepected

	  speculative store bypassing.



	  Work around this problem by placing a speculation barrier after

	  kernel changes to SSBS. The presence of the SSBS special-purpose

	  register is hidden from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such

	  that userspace will use the PR_SPEC_STORE_BYPASS prctl to change

	  SSBS.



	  If unsure, say Y.



config ARM64_ERRATUM_3312417

	bool "Neoverse-V3: 3312417: workaround for MSR SSBS not self-synchronizing"

	select ARM64_WORKAROUND_SPECULATIVE_SSBS

	default y

	help

	  This option adds the workaround for ARM Neoverse-V3 erratum 3312417.



	  On affected cores "MSR SSBS, #0" instructions may not affect

	  subsequent speculative instructions, which may permit unexepected

	  speculative store bypassing.



	  Work around this problem by placing a speculation barrier after

	  kernel changes to SSBS. The presence of the SSBS special-purpose

	  register is hidden from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such

	  that userspace will use the PR_SPEC_STORE_BYPASS prctl to change

	  SSBS.



	  If unsure, say Y.





config CAVIUM_ERRATUM_22375

	bool "Cavium erratum 22375, 24313"

	default y

arch/arm64/include/asm/asm-bug.h

+1 −0
Original line number Diff line number Diff line
@@ -28,6 +28,7 @@ 
	14470:	.long 14471f - .;			\

_BUGVERBOSE_LOCATION(__FILE__, __LINE__)		\

		.short flags; 				\

		.align 2;				\

		.popsection;				\

	14471:

#else

arch/arm64/include/asm/barrier.h

+4 −0
Original line number Diff line number Diff line
@@ -40,6 +40,10 @@ 
 */

#define dgh()		asm volatile("hint #6" : : : "memory")



#define spec_bar()	asm volatile(ALTERNATIVE("dsb nsh\nisb\n",		\

						 SB_BARRIER_INSN"nop\n",	\

						 ARM64_HAS_SB))



#ifdef CONFIG_ARM64_PSEUDO_NMI

#define pmr_sync()						\

	do {							\

arch/arm64/include/asm/cpucaps.h

+2 −0
Original line number Diff line number Diff line
@@ -58,6 +58,8 @@ cpucap_is_possible(const unsigned int cap) 
		return IS_ENABLED(CONFIG_NVIDIA_CARMEL_CNP_ERRATUM);

	case ARM64_WORKAROUND_REPEAT_TLBI:

		return IS_ENABLED(CONFIG_ARM64_WORKAROUND_REPEAT_TLBI);

	case ARM64_WORKAROUND_SPECULATIVE_SSBS:

		return IS_ENABLED(CONFIG_ARM64_WORKAROUND_SPECULATIVE_SSBS);

	}



	return true;