Commit 2dc25093 authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
Browse files

Merge tag 'counter-fixes-for-6.14' of... 

Merge tag 'counter-fixes-for-6.14' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/wbg/counter into char-misc-linus

William writes:

Counter fixes for 6.14

A fix to resolve a timeout error during counter enable leading to a
false report of 'enable' state in stm32-lptimer-cnt. A fix to properly
intialize counter channels during probe to avoid operating under an
undefined state in microchip-tcb-capture.

* tag 'counter-fixes-for-6.14' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/wbg/counter:
  counter: microchip-tcb-capture: Fix undefined counter channel state on probe
  counter: stm32-lptimer-cnt: fix error handling when enabling
parents 80e54e84 c0c9c734

drivers/counter/microchip-tcb-capture.c

+19 −0
Original line number Diff line number Diff line
@@ -368,6 +368,25 @@ static int mchp_tc_probe(struct platform_device *pdev) 
			channel);

	}



	/* Disable Quadrature Decoder and position measure */

	ret = regmap_update_bits(regmap, ATMEL_TC_BMR, ATMEL_TC_QDEN | ATMEL_TC_POSEN, 0);

	if (ret)

		return ret;



	/* Setup the period capture mode */

	ret = regmap_update_bits(regmap, ATMEL_TC_REG(priv->channel[0], CMR),

				 ATMEL_TC_WAVE | ATMEL_TC_ABETRG | ATMEL_TC_CMR_MASK |

				 ATMEL_TC_TCCLKS,

				 ATMEL_TC_CMR_MASK);

	if (ret)

		return ret;



	/* Enable clock and trigger counter */

	ret = regmap_write(regmap, ATMEL_TC_REG(priv->channel[0], CCR),

			   ATMEL_TC_CLKEN | ATMEL_TC_SWTRG);

	if (ret)

		return ret;



	priv->tc_cfg = tcb_config;

	priv->regmap = regmap;

	counter->name = dev_name(&pdev->dev);

drivers/counter/stm32-lptimer-cnt.c

+15 −9
Original line number Diff line number Diff line
@@ -58,37 +58,43 @@ static int stm32_lptim_set_enable_state(struct stm32_lptim_cnt *priv, 
		return 0;

	}



	ret = clk_enable(priv->clk);

	if (ret)

		goto disable_cnt;



	/* LP timer must be enabled before writing CMP & ARR */

	ret = regmap_write(priv->regmap, STM32_LPTIM_ARR, priv->ceiling);

	if (ret)

		return ret;

		goto disable_clk;



	ret = regmap_write(priv->regmap, STM32_LPTIM_CMP, 0);

	if (ret)

		return ret;

		goto disable_clk;



	/* ensure CMP & ARR registers are properly written */

	ret = regmap_read_poll_timeout(priv->regmap, STM32_LPTIM_ISR, val,

				       (val & STM32_LPTIM_CMPOK_ARROK) == STM32_LPTIM_CMPOK_ARROK,

				       100, 1000);

	if (ret)

		return ret;

		goto disable_clk;



	ret = regmap_write(priv->regmap, STM32_LPTIM_ICR,

			   STM32_LPTIM_CMPOKCF_ARROKCF);

	if (ret)

		return ret;

		goto disable_clk;



	ret = clk_enable(priv->clk);

	if (ret) {

		regmap_write(priv->regmap, STM32_LPTIM_CR, 0);

		return ret;

	}

	priv->enabled = true;



	/* Start LP timer in continuous mode */

	return regmap_update_bits(priv->regmap, STM32_LPTIM_CR,

				  STM32_LPTIM_CNTSTRT, STM32_LPTIM_CNTSTRT);



disable_clk:

	clk_disable(priv->clk);

disable_cnt:

	regmap_write(priv->regmap, STM32_LPTIM_CR, 0);



	return ret;

}



static int stm32_lptim_setup(struct stm32_lptim_cnt *priv, int enable)