Commit 2dd18279 authored by Robert Richter's avatar Robert Richter Committed by Dan Williams
Browse files

cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_state 



Same as for ports and dports, also store the endpoint's Component
Register mappings, use struct cxl_dev_state for that.

Keep the Component Register base address @component_reg_phys a bit to
not break functionality. It will be removed after the transition in a
later patch.

Signed-off-by: default avatarTerry Bowman <terry.bowman@amd.com>
Signed-off-by: default avatarRobert Richter <rrichter@amd.com>
Reviewed-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: default avatarDave Jiang <dave.jiang@intel.com>
Link: https://lore.kernel.org/r/20231018171713.1883517-7-rrichter@amd.com


Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
parent 4d758764

drivers/cxl/core/mbox.c

+2 −0
Original line number Diff line number Diff line
@@ -1377,6 +1377,8 @@ struct cxl_memdev_state *cxl_memdev_state_create(struct device *dev) 
	mutex_init(&mds->mbox_mutex);

	mutex_init(&mds->event.log_lock);

	mds->cxlds.dev = dev;

	mds->cxlds.reg_map.host = dev;

	mds->cxlds.reg_map.resource = CXL_RESOURCE_NONE;

	mds->cxlds.type = CXL_DEVTYPE_CLASSMEM;



	return mds;

drivers/cxl/cxlmem.h

+2 −0
Original line number Diff line number Diff line
@@ -397,6 +397,7 @@ enum cxl_devtype { 
 *

 * @dev: The device associated with this CXL state

 * @cxlmd: The device representing the CXL.mem capabilities of @dev

 * @reg_map: component and ras register mapping parameters

 * @regs: Parsed register blocks

 * @cxl_dvsec: Offset to the PCIe device DVSEC

 * @rcd: operating in RCD mode (CXL 3.0 9.11.8 CXL Devices Attached to an RCH)
@@ -411,6 +412,7 @@ enum cxl_devtype { 
struct cxl_dev_state {

	struct device *dev;

	struct cxl_memdev *cxlmd;

	struct cxl_register_map reg_map;

	struct cxl_regs regs;

	int cxl_dvsec;

	bool rcd;

drivers/cxl/pci.c

+5 −4
Original line number Diff line number Diff line
@@ -835,15 +835,16 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 
	 * still be useful for management functions so don't return an error.

	 */

	cxlds->component_reg_phys = CXL_RESOURCE_NONE;

	rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, &map);

	rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT,

				&cxlds->reg_map);

	if (rc)

		dev_warn(&pdev->dev, "No component registers (%d)\n", rc);

	else if (!map.component_map.ras.valid)

	else if (!cxlds->reg_map.component_map.ras.valid)

		dev_dbg(&pdev->dev, "RAS registers not found\n");



	cxlds->component_reg_phys = map.resource;

	cxlds->component_reg_phys = cxlds->reg_map.resource;



	rc = cxl_map_component_regs(&map, &cxlds->regs.component,

	rc = cxl_map_component_regs(&cxlds->reg_map, &cxlds->regs.component,

				    BIT(CXL_CM_CAP_CAP_ID_RAS));

	if (rc)

		dev_dbg(&pdev->dev, "Failed to map RAS capability.\n");