Commit 2df8e64e authored by Ivan Vecera's avatar Ivan Vecera Committed by Jakub Kicinski
Browse files

dpll: Add basic Microchip ZL3073x support



Microchip Azurite ZL3073x represents chip family providing DPLL
and optionally PHC (PTP) functionality. The chips can be connected
be connected over I2C or SPI bus.

They have the following characteristics:
* up to 5 separate DPLL units (channels)
* 5 synthesizers
* 10 input pins (references)
* 10 outputs
* 20 output pins (output pin pair shares one output)
* Each reference and output can operate in either differential or
  single-ended mode (differential mode uses 2 pins)
* Each output is connected to one of the synthesizers
* Each synthesizer is driven by one of the DPLL unit

The device uses 7-bit addresses and 8-bits values. It exposes 8-, 16-,
32- and 48-bits registers in address range <0x000,0x77F>. Due to 7bit
addressing, the range is organized into pages of 128 bytes, with each
page containing a page selector register at address 0x7F.
For reading/writing multi-byte registers, the device supports bulk
transfers.

Add basic functionality to access device registers, probe functionality
both I2C and SPI cases and add devlink support to provide info and
to set clock ID parameter.

Signed-off-by: default avatarIvan Vecera <ivecera@redhat.com>
Reviewed-by: default avatarJiri Pirko <jiri@nvidia.com>
Link: https://patch.msgid.link/20250704182202.1641943-6-ivecera@redhat.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent de9ccf22
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+1 −0
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@@ -98,3 +98,4 @@ parameters, info versions, and other features it supports.
   iosm
   octeontx2
   sfc
   zl3073x
+51 −0
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.. SPDX-License-Identifier: GPL-2.0

=======================
zl3073x devlink support
=======================

This document describes the devlink features implemented by the ``zl3073x``
device driver.

Parameters
==========

.. list-table:: Generic parameters implemented
   :widths: 5 5 90

   * - Name
     - Mode
     - Notes
   * - ``clock_id``
     - driverinit
     - Set the clock ID that is used by the driver for registering DPLL devices
       and pins.

Info versions
=============

The ``zl3073x`` driver reports the following versions

.. list-table:: devlink info versions implemented
    :widths: 5 5 5 90

    * - Name
      - Type
      - Example
      - Description
    * - ``asic.id``
      - fixed
      - 1E94
      - Chip identification number
    * - ``asic.rev``
      - fixed
      - 300
      - Chip revision number
    * - ``fw``
      - running
      - 7006
      - Firmware version number
    * - ``custom_cfg``
      - running
      - 1.3.0.1
      - Device configuration version customized by OEM
+8 −0
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@@ -16514,6 +16514,14 @@ L: linux-wireless@vger.kernel.org
S:	Supported
F:	drivers/net/wireless/microchip/
MICROCHIP ZL3073X DRIVER
M:	Ivan Vecera <ivecera@redhat.com>
M:	Prathosh Satish <Prathosh.Satish@microchip.com>
L:	netdev@vger.kernel.org
S:	Supported
F:	Documentation/devicetree/bindings/dpll/microchip,zl30731.yaml
F:	drivers/dpll/zl3073x/
MICROSEMI MIPS SOCS
M:	Alexandre Belloni <alexandre.belloni@bootlin.com>
M:	UNGLinuxDriver@microchip.com
+2 −2
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@@ -77,6 +77,8 @@ source "drivers/pps/Kconfig"

source "drivers/ptp/Kconfig"

source "drivers/dpll/Kconfig"

source "drivers/pinctrl/Kconfig"

source "drivers/gpio/Kconfig"
@@ -245,6 +247,4 @@ source "drivers/hte/Kconfig"

source "drivers/cdx/Kconfig"

source "drivers/dpll/Kconfig"

endmenu
+6 −0
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@@ -3,5 +3,11 @@
# Generic DPLL drivers configuration
#

menu "DPLL device support"

config DPLL
	bool

source "drivers/dpll/zl3073x/Kconfig"

endmenu
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