Commit 2e3ed20c authored by Lucas Stach's avatar Lucas Stach Committed by David S. Miller
Browse files

net: dsa: microchip: lan937x: disable VPHY support 

As described by the microchip article "LAN937X - The required
configuration for the external MAC port to operate at RGMII-to-RGMII
1Gbps link speed." [1]:

"When VPHY is enabled, the auto-negotiation process following IEEE 802.3
standard will be triggered and will result in RGMII-to-RGMII signal
failure on the interface because VPHY will try to poll the PHY status
that is not available in the scenario of RGMII-to-RGMII connection
(normally the link partner is usually an external processor).

Note that when VPHY fails on accessing PHY registers, it will fall back
to 100Mbps speed, it indicates disabling VPHY is optional if you only
need the port to link at 100Mbps speed.

Again, VPHY must and can only be disabled by writing VPHY_DISABLE bit in
the register below as there is no strapping pin for the control."

This patch was tested on LAN9372, so far it seems to not to affect VPHY
based clock crossing optimization for the ports with integrated PHYs.

[1]: https://microchip.my.site.com/s/article/LAN937X-The-required-configuration-for-the-external-MAC-port-to-operate-at-RGMII-to-RGMII-1Gbps-link-speed



Signed-off-by: default avatarLucas Stach <l.stach@pengutronix.de>
Signed-off-by: default avatarOleksij Rempel <o.rempel@pengutronix.de>
Reviewed-by: default avatarVladimir Oltean <olteanv@gmail.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent c3db3946

drivers/net/dsa/microchip/lan937x_main.c

+3 −0
Original line number Diff line number Diff line
@@ -390,6 +390,9 @@ int lan937x_setup(struct dsa_switch *ds) 
	lan937x_cfg(dev, REG_SW_GLOBAL_OUTPUT_CTRL__1,

		    (SW_CLK125_ENB | SW_CLK25_ENB), true);



	/* Disable global VPHY support. Related to CPU interface only? */

	ksz_rmw32(dev, REG_SW_CFG_STRAP_OVR, SW_VPHY_DISABLE, SW_VPHY_DISABLE);



	return 0;

}

drivers/net/dsa/microchip/lan937x_reg.h

+4 −0
Original line number Diff line number Diff line
@@ -37,6 +37,10 @@ 
#define SW_CLK125_ENB			BIT(1)

#define SW_CLK25_ENB			BIT(0)



/* 2 - PHY Control */

#define REG_SW_CFG_STRAP_OVR		0x0214

#define SW_VPHY_DISABLE			BIT(31)



/* 3 - Operation Control */

#define REG_SW_OPERATION		0x0300