Commit 2f0d5eca authored by Lijo Lazar's avatar Lijo Lazar Committed by Alex Deucher
Browse files

drm/amd/pm: Add debug message callback 



Add callback in message control to send message through debug mailbox.

Signed-off-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Reviewed-by: default avatarAsad Kamal <asad.kamal@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent b9b393c6

drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h

+12 −0
Original line number Diff line number Diff line
@@ -557,6 +557,9 @@ struct cmn2asic_mapping { 
#define SMU_MSG_FLAG_ASYNC	BIT(0) /* Async send - skip post-poll */

#define SMU_MSG_FLAG_LOCK_HELD	BIT(1) /* Caller holds ctl->lock */



/* smu_msg_ctl flags */

#define SMU_MSG_CTL_DEBUG_MAILBOX	BIT(0) /* Debug mailbox supported */



struct smu_msg_ctl;

/**

 * struct smu_msg_config - IP-level register configuration
@@ -564,12 +567,18 @@ struct smu_msg_ctl; 
 * @resp_reg: Response register offset

 * @arg_regs: Argument register offsets (up to SMU_MSG_MAX_ARGS)

 * @num_arg_regs: Number of argument registers available

 * @debug_msg_reg: Debug message register offset

 * @debug_resp_reg: Debug response register offset

 * @debug_param_reg: Debug parameter register offset

 */

struct smu_msg_config {

	u32 msg_reg;

	u32 resp_reg;

	u32 arg_regs[SMU_MSG_MAX_ARGS];

	int num_arg_regs;

	u32 debug_msg_reg;

	u32 debug_resp_reg;

	u32 debug_param_reg;

};



/**
@@ -597,11 +606,13 @@ struct smu_msg_args { 
 * @send_msg: send message protocol

 * @wait_response: wait for response (for split send/wait cases)

 * @decode_response: Convert response register value to errno

 * @send_debug_msg: send debug message

 */

struct smu_msg_ops {

	int (*send_msg)(struct smu_msg_ctl *ctl, struct smu_msg_args *args);

	int (*wait_response)(struct smu_msg_ctl *ctl, u32 timeout_us);

	int (*decode_response)(u32 resp);

	int (*send_debug_msg)(struct smu_msg_ctl *ctl, u32 msg, u32 param);

};



/**
@@ -617,6 +628,7 @@ struct smu_msg_ctl { 
	const struct smu_msg_ops *ops;

	const struct cmn2asic_msg_mapping *message_map;

	u32 default_timeout;

	u32 flags;

};



struct stb_context {

drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c

+20 −0
Original line number Diff line number Diff line
@@ -83,6 +83,25 @@ static const char *smu_get_message_name(struct smu_context *smu, 


#define SMU_RESP_UNEXP (~0U)



static int smu_msg_v1_send_debug_msg(struct smu_msg_ctl *ctl, u32 msg, u32 param)

{

	struct amdgpu_device *adev = ctl->smu->adev;

	struct smu_msg_config *cfg = &ctl->config;



	if (!(ctl->flags & SMU_MSG_CTL_DEBUG_MAILBOX))

		return -EOPNOTSUPP;



	mutex_lock(&ctl->lock);



	WREG32(cfg->debug_param_reg, param);

	WREG32(cfg->debug_msg_reg, msg);

	WREG32(cfg->debug_resp_reg, 0);



	mutex_unlock(&ctl->lock);



	return 0;

}



static int __smu_cmn_send_debug_msg(struct smu_context *smu,

			       u32 msg,

			       u32 param)
@@ -541,6 +560,7 @@ const struct smu_msg_ops smu_msg_v1_ops = { 
	.send_msg = smu_msg_v1_send_msg,

	.wait_response = smu_msg_v1_wait_response,

	.decode_response = smu_msg_v1_decode_response,

	.send_debug_msg = smu_msg_v1_send_debug_msg,

};



int smu_msg_wait_response(struct smu_msg_ctl *ctl, u32 timeout_us)