Commit 2f602531 authored by Jouni Högander's avatar Jouni Högander
Browse files

drm/panel replay: Add edp1.5 Panel Replay bits and register 



Add PANEL_REPLAY_CONFIGURATION_2 register and some missing Panel Replay
bits.

Signed-off-by: default avatarJouni Högander <jouni.hogander@intel.com>
Reviewed-by: default avatarAnimesh Manna <animesh.manna@intel.com>
Acked-by: default avatarMaxime Ripard <mripard@kernel.org>
Acked-by: default avatarMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240528114455.175961-3-jouni.hogander@intel.com
parent 73baf72e

include/drm/display/drm_dp.h

+13 −3
Original line number Diff line number Diff line
@@ -547,6 +547,7 @@ 
#define DP_PANEL_REPLAY_CAP				0x0b0  /* DP 2.0 */

# define DP_PANEL_REPLAY_SUPPORT			(1 << 0)

# define DP_PANEL_REPLAY_SU_SUPPORT			(1 << 1)

# define DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT	(1 << 2) /* eDP 1.5 */



#define DP_PANEL_PANEL_REPLAY_CAPABILITY		0xb1

# define DP_PANEL_PANEL_REPLAY_SU_GRANULARITY_REQUIRED	(1 << 5)
@@ -734,11 +735,20 @@ 


#define PANEL_REPLAY_CONFIG                             0x1b0  /* DP 2.0 */

# define DP_PANEL_REPLAY_ENABLE                         (1 << 0)

# define DP_PANEL_REPLAY_VSC_SDP_CRC_EN                 (1 << 1) /* eDP 1.5 */

# define DP_PANEL_REPLAY_UNRECOVERABLE_ERROR_EN         (1 << 3)

# define DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN           (1 << 4)

# define DP_PANEL_REPLAY_ACTIVE_FRAME_CRC_ERROR_EN      (1 << 5)

# define DP_PANEL_REPLAY_SU_ENABLE                      (1 << 6)



#define PANEL_REPLAY_CONFIG2                                     0x1b1 /* eDP 1.5 */

# define DP_PANEL_REPLAY_SINK_REFRESH_RATE_UNLOCK_GRANTED	 (1 << 0)

# define DP_PANEL_REPLAY_CRC_VERIFICATION			 (1 << 1)

# define DP_PANEL_REPLAY_SU_Y_GRANULARITY_EXTENDED_EN		 (1 << 2)

# define DP_PANEL_REPLAY_SU_Y_GRANULARITY_EXTENDED_VAL_SEL_SHIFT 3

# define DP_PANEL_REPLAY_SU_Y_GRANULARITY_EXTENDED_VAL_SEL_MASK  (0xf << 3)

# define DP_PANEL_REPLAY_SU_REGION_SCANLINE_CAPTURE		 (1 << 7)



#define DP_PAYLOAD_ALLOCATE_SET		    0x1c0

#define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1

#define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2