Commit 2f69e545 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Abhinav Kumar
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drm/msm/dpu: skip watchdog timer programming through TOP on >= SM8450 



The SM8450 and later chips have DPU_MDP_PERIPH_0_REMOVED feature bit
set, which means that those platforms have dropped some of the
registers, including the WD TIMER-related ones. Stop providing the
callback to program WD timer on those platforms.

Fixes: 100d7ef6 ("drm/msm/dpu: add support for SM8450")
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: default avatarAbhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/628874/
Link: https://lore.kernel.org/r/20241214-dpu-drop-features-v1-1-988f0662cb7e@linaro.org


Signed-off-by: default avatarAbhinav Kumar <quic_abhinavk@quicinc.com>
parent 669c2856

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c

+1 −1
Original line number Diff line number Diff line
@@ -272,7 +272,7 @@ static void _setup_mdp_ops(struct dpu_hw_mdp_ops *ops, 


	if (cap & BIT(DPU_MDP_VSYNC_SEL))

		ops->setup_vsync_source = dpu_hw_setup_vsync_sel;

	else

	else if (!(cap & BIT(DPU_MDP_PERIPH_0_REMOVED)))

		ops->setup_vsync_source = dpu_hw_setup_wd_timer;



	ops->get_safe_status = dpu_hw_get_safe_status;