Commit 2f8acf78 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'v6.10-rockchip-clk1' of... 

Merge tag 'v6.10-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip

Pull some small Rockchip clk driver updates from Heiko Stuebner:

 - A new PLL rate and missing mux on rk3568
 - A missing reset line on rk3588
 - Removal of an unused field in struct rockchip_mmc_clock

* tag 'v6.10-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: rk3568: Add PLL rate for 724 MHz
  clk: rockchip: Remove an unused field in struct rockchip_mmc_clock
  clk: rockchip: rk3588: Add reset line for HDMI Receiver
  clk: rockchip: rk3568: Add missing USB480M_PHY mux
  dt-bindings: reset: Define reset id used for HDMI Receiver
  dt-bindings: clock: rockchip: add USB480M_PHY mux
parents 4cece764 f513991b

drivers/clk/rockchip/clk-mmc-phase.c

+0 −1
Original line number Diff line number Diff line
@@ -14,7 +14,6 @@ 
struct rockchip_mmc_clock {

	struct clk_hw	hw;

	void __iomem	*reg;

	int		id;

	int		shift;

	int		cached_phase;

	struct notifier_block clk_rate_change_nb;

drivers/clk/rockchip/clk-rk3568.c

+5 −0
Original line number Diff line number Diff line
@@ -64,6 +64,7 @@ static struct rockchip_pll_rate_table rk3568_pll_rates[] = { 
	RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),

	RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),

	RK3036_PLL_RATE(800000000, 3, 200, 2, 1, 1, 0),

	RK3036_PLL_RATE(724000000, 3, 181, 2, 1, 1, 0),

	RK3036_PLL_RATE(700000000, 3, 350, 4, 1, 1, 0),

	RK3036_PLL_RATE(696000000, 1, 116, 4, 1, 1, 0),

	RK3036_PLL_RATE(600000000, 1, 100, 4, 1, 1, 0),
@@ -215,6 +216,7 @@ static const struct rockchip_cpuclk_reg_data rk3568_cpuclk_data = { 


PNAME(mux_pll_p)			= { "xin24m" };

PNAME(mux_usb480m_p)			= { "xin24m", "usb480m_phy", "clk_rtc_32k" };

PNAME(mux_usb480m_phy_p)		= { "clk_usbphy0_480m", "clk_usbphy1_480m"};

PNAME(mux_armclk_p)			= { "apll", "gpll" };

PNAME(clk_i2s0_8ch_tx_p)		= { "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_frac", "i2s0_mclkin", "xin_osc0_half" };

PNAME(clk_i2s0_8ch_rx_p)		= { "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_frac", "i2s0_mclkin", "xin_osc0_half" };
@@ -485,6 +487,9 @@ static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = { 
	MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,

			RK3568_MODE_CON0, 14, 2, MFLAGS),



	MUX(USB480M_PHY, "usb480m_phy", mux_usb480m_phy_p, CLK_SET_RATE_PARENT,

			RK3568_MISC_CON2, 15, 1, MFLAGS),



	/* PD_CORE */

	COMPOSITE(0, "sclk_core_src", apll_gpll_npll_p, CLK_IGNORE_UNUSED,

			RK3568_CLKSEL_CON(2), 8, 2, MFLAGS, 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,

drivers/clk/rockchip/rst-rk3588.c

+1 −0
Original line number Diff line number Diff line
@@ -577,6 +577,7 @@ static const int rk3588_register_offset[] = { 


	/* SOFTRST_CON59 */

	RK3588_CRU_RESET_OFFSET(SRST_A_HDCP1_BIU, 59, 6),

	RK3588_CRU_RESET_OFFSET(SRST_A_HDMIRX_BIU, 59, 7),

	RK3588_CRU_RESET_OFFSET(SRST_A_VO1_BIU, 59, 8),

	RK3588_CRU_RESET_OFFSET(SRST_H_VOP1_BIU, 59, 9),

	RK3588_CRU_RESET_OFFSET(SRST_H_VOP1_S_BIU, 59, 10),

include/dt-bindings/clock/rk3568-cru.h

+1 −0
Original line number Diff line number Diff line
@@ -78,6 +78,7 @@ 
#define CPLL_333M		9

#define ARMCLK			10

#define USB480M			11

#define USB480M_PHY		12

#define ACLK_CORE_NIU2BUS	18

#define CLK_CORE_PVTM		19

#define CLK_CORE_PVTM_CORE	20

include/dt-bindings/reset/rockchip,rk3588-cru.h

+2 −0
Original line number Diff line number Diff line
@@ -751,4 +751,6 @@ 
#define SRST_P_TRNG_CHK			658

#define SRST_TRNG_S			659



#define SRST_A_HDMIRX_BIU		660



#endif